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MIPI TWP Adaptor IIP

MIPI Trace Wrapper Protocol Adaptor IIP

MIPI TWP Adaptor IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech MIPI TWP Adaptor IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Ideal for mobile, automotive, and IoT applications requiring high-bandwidth camera and display interfaces. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Low Power & High Efficiency: Optimized for mobile and battery-operated devices with advanced power gating and low-leakage architecture.

Silicon Proven: Validated on leading foundry nodes (5nm, 7nm, 12nm, 28nm), ensuring reduced integration risk.

Comprehensive Support: Full compliance with latest MIPI Alliance specifications, including CSI-2, DSI-2, and I3C.

Flexible Licensing: Cost-effective, royalty-free licensing models compared to restrictive tier-1 vendor options.

FEATURES
  • MIPI TWP v1.1 Adaptor Compliant with MIPI TWP version 1.1 specification.
  • Full MIPI Debug functionality.
  • Supports all Debug CCC's and Opcodes Supports following three layear -Layer T1: Flow Control. Supported by the TWP Padding Packet. -Layer T2: Alignment Synchronization. Supported by the TWP Frame Synchronization Packet. -Layer T3: Data. Supported by the TWP Frame
  • Allows up to 111 source trace streams to be represented as a single stream and later separated by either hardware or software.
  • Supports Error handling and flushing mechanisim.
  • Fully synthesizable.
  • Static synchronous design.
  • Positive edge clocking and no internal tri-states.
  • Scan test ready.
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors.
FUNCTIONAL DESCRIPTION

CORE: CORE module interconnects all the sub-modules in the MIPI TWP Adaptor IIP (CSR, TWP). Ports of core module are the top level ports for the MIPI TWP Adaptor IIP.

CSR : CSR module holds control, status, interrupt, configuration registers for the MIPI TWP Adaptor IIP which can be accessed via AMBA/Custom interface.

TWP : TWP module interconnects the ATB SLAVE used to Receive the Trace data from ATB SLAVE and Transmit the Formatted trace data to Network layer OB FIFO.

ATB SLAVE : ATB SLAVE collects protocol agnostic traces from trace source stream.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesSystem Clock FrequencyNetwork Clock FrequencyATB Clock Frequency
TSMC 28nm8.35K240.038MHz1GHz800MHz

FPGA Device and FamilyLogic ResourcesSystem Clock FrequencyNetwork Clock FrequencyATB Clock Frequency
AMD Virtex Ultrascale+51685 LUT's100MHz100MHz100MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.