The SivaKali Tech USB PD IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Perfect for consumer electronics, peripherals, and embedded IoT devices. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.
COMPETITIVE ADVANTAGE
Certified Interoperability: Extensive testing against standard USB hosts and devices to guarantee plug-and-play compatibility.
Highly Configurable: Flexible endpoint configuration and FIFO sizing to optimize area vs. performance trade-offs.
Low Power Modes: Aggressive power management supporting Suspend/Resume and remote wakeup capabilities.
Legacy Support: Backward compatibility ensuring seamless operation with older USB revisions.
FEATURES
Compliant with USB Power Delivery Specification 3.1/3.0/2.0 and 1.0
Compliant with USB Type-C Cable and Connector Specification 3.0/2.0 and 1.0
Supports Cable plug communication
Supports all Resets: Hard, Soft and Cable Resets
Supports all types of packets.
Supports BFSK and BMC signaling of physical layer
Support BIST.
Supports Timers as per specification
Supports Counters as per specification
Supports data role swap and power role swap
Supports Structured and Unstructured VDM
Supports Device and System Policy
Supports injecting timing variations in physical layer.
Supports all Swappings: Power role, Data role, Fast power role and Vconn swap
Supports chunked transaction
Supports included extended power supply capabilities and status.
Fully synthesizable.
Static synchronous design.
Positive edge clocking and no internal tri-states.
Scan test ready.
Simple host interfaces enable straightforward integration with microcontrollers and application processors. Available as Additional feature at extra cost
ISO26262 Automotive safety(ASIL B/D)
This core achieves ASIL B and can be made to achieve ASIL D as per ISO26262
Memories with ECC
Basic Firmware - Linux driver
XML Support
Customer SoC I/F
FUNCTIONAL DESCRIPTION
CORE: Core module interconnects all the sub-modules in the USB_PD IP. Ports of core module are the top level ports for the USB_PD IP.
RPRESCALER: Rprescaler interface module recovers the clock from preamble data received and generates clock to sample the received data.
TPRESCALER: Tprescaler generates clock based on the prescaler value
TX_FSM: Tx fsm calculates the cyclic redundancy check value, transmits preamble patterns and encodes sop and data then it sends these 4 bit parallel data to encoder.
RX_FSM: Rx fsm checks the cyclic redundancy check value integrity and decodes the sop and data.
ENCODER: Encoder encodes these 4 bit parallel data to 5 bit encoded then serializes and transmits the data. DECODER: Decoder decodes the 5bit encoded data to 4 bit decoded data.
ASIC AND FPGA IMPLEMENTATION
ASIC Technology
Logic Resources
System Clock Frequency
TSMC 28nm
24.24K
800MHz
FPGA Device and Family
Logic Resources
System Clock Frequency
AMD Virtex-7 FPGA(xc7vx485tffg1761-2)
2407 LUT's
800MHz
LICENSING OPTIONS
Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.
