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ETHERNET Switch IIP

ETHERNET Switch IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech ETHERNET Switch IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Designed for data center, enterprise networking, and industrial automation environments. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Low Latency Architecture: Engineered for real-time applications with deterministic latency, ideal for TSN (Time Sensitive Networking).

Scalable Performance: Seamless migration paths from 10M to 800G, supporting a wide range of networking requirements.

Robust Compliance: Fully compliant with IEEE 802.3 standards, ensuring interoperability with standard network equipment.

Integrated Offload: Advanced TCP/UDP offload engines (TOE) to reduce host processor overhead.

FEATURES
  • Compliant with IEEE Standard 802.3-2022 Specification
  • Supports Full-duplex and Half-duplex 10M/100M/1G Ethernet interfaces
  • Supports 10G/25G/50G/40G and 100G Ethernet interfaces
  • Supports MII/GMII/RGMII/QSGMII/USXGMII Physical Layer device (PHY) interfaces
  • Supports different data rate for each port
  • Supports Dynamic MAC Table with automatic MAC addresses learning and aging
  • Supports Static MAC Table
  • Supports Jumbo Frame Management
  • Supports Ethertype Based Switching
  • Supports Ingress Port Mirroring
  • Supports Broadcast/Multicast Storm protection
  • Supports Per-Port Rate limiting (Broadcast, Multicast and Unicast traffic)
  • Supports timing synchronization as per IEEE Standard 1588-2008(PTP) and IEEE Standard 802.1AS(GPTP) Supports Multicast Frame Filtering
  • Supports Switching Portmask
  • Supports Port-based VLAN
  • Supports QoS - Priorities(PCP-802.1p,DSCP TOS, Ethertype)
  • Supports DSA (Distributed Switching Architecture) tagging
  • Supports MDIO, AXI4-Lite or CoE(Configuration-over-Ethernet) SoC interfaces
  • Supports MRP (Software stack not required)
    • Ring Manager (MRM)
    • Ring Client (MRC)
  • Supports DLR (Software stack not required)
    • Beacon Based Node
    • Supervisor Node
  • Supports Preemption as per IEEE Standard 802.1Qbu and IEEE Standard 802.3br Interspersing Express Traffic
  • Supports Traffic Scheduling - IEEE Standard 802.1Qbv and IEEE Standard 802.1Qav
  • Supports class based flow control and class based FIFO to store each class, total 8 class - IEEE Standard 802.1Q
  • In house UNH compliance tested Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors
FUNCTIONAL DESCRIPTION

Node: Each node consists of MAC, ingress and egress. Ingress processing receives frames from Ethernet and transfers them to the buffer memory of egress.All transmitter process done here in the egress for the each ports. The MAC will receive the packet from the another device

Address Learning: Switch updates the MAC address table automatically according to the source MAC address information in the received Ethernet frames.The Address learning updates the MAC Address Table when the receive port of the frame is in Forwarding or Learning state.It process for the source address of a received Ethernet frame.

Arbiter: The Arbiter will decide whether the incoming SoC signals address and data information to which node’s CSR.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesClock FrequencySystem Clock FrequencyMAC Clock Frequency
TSMC 28nm419.25K167.66MHz167.66MHz125MHz
UMSC 55nm823.52K167.66MHz167.66MHz125MHz
SMIC 40nm598.92K167.66MHz167.66MHz125MHz

FPGA Device and FamilyLogic ResourcesClock FrequencySystem Clock FrequencyMAC Clock Frequency
AMD-xcvu9p-flga2104-2L-e69875 LUT's167.66MHz167.66MHz125MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.