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HDMI eARC Transmitter IIP

High Definition Multimedia Interface - Enhanced Audio Return Channel Transmitter IIP

HDMI eARC Transmitter IIP

Overview

It supports two modes:

1.Differential Mode Audio Channel

2.Common Mode Data Channel

COMPETITIVE ADVANTAGE

The SivaKali Tech HDMI eARC Transmitter IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Delivering premium visual experiences for digital signage, broadcast, and consumer displays. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

High Quality Compression: Visually lossless compression algorithms optimized for minimal silicon area.

Real-Time Performance: Ultra-low latency processing suitable for live streaming and interactive applications.

Multi-Standard Support: Configurable to support various resolutions, frame rates, and color formats.

Power Efficient: Architecture optimized to minimize power consumption for portable multimedia devices.

FEATURES
  • HDMI eARC Transmitter IIP
  • Fully compliant with the HDMI eARC Transmitter specification as defined in the HDMI version 2.1b specification and ensures standard-adherent operation across all supported configurations.
  • Supports configurable audio channel count from 2 to 32 channels.
  • Supports variable audio sample words lengths of 16-bit, 20-bit and 24-bit.
  • Supports audio sample rates from 32kHz to 192kHz.
  • Supports the transmission of the following encrypted and unencrypted audio formats:
    • 2-channel L-PCM.
    • Multi-channel L-PCM.
    • IEC 61937(compressed audio).
    • One bit audio.
  • Supports single-ended non-differential split outputs for flexible integration.
  • Performs bi-phase mark encoding and falling-edge modulation.
  • Dynamically supports seamless Audio Format Change operations.
  • Manages the following bidirectional functions over the eARC Common Mode Data Channel:
    • Discovery and Disconnect protocols.
    • Heartbeat monitoring.
    • Status bits transmission/reception.
    • Audio Latency Control.
    • Capabilities Data Structure exchange
  • Supports the insertion of audio channel status and user bits into outgoing stream.
  • Assembles and transmits ACP, ISRC1 and ISRC2 U-bit messages structures.
  • Incorporates Error Correcting Code(ECC) generation and encoding on both the eARC Common mode data channel and the high-speed differential mode channel.
  • Fully synthesizable.
  • Static synchronous design.
  • Positive edge clocking and no internal tri-states.
  • Scan test ready.
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors.
FUNCTIONAL DESCRIPTION

CSR: Contains all configuration registers used to monitor status and control the RTL functionality.

CONTROL ENCODER: Encodes the outgoing payload from control transmit FSM into a biphase-mark serialized bitstream for transmission over the Common mode data channel.

CONTROL TRANSMIT FSM: Manages the overall state machine for transmitting discovery, capability and status information to the downstream eARC Receiver.

CONTROL DECODER: Decoded incoming responses(such as heartbeat acknowledgements or capability data) from the eARC receiver over the control channel.

CONTROL RECEIVE FSM: Validates the incoming messages decoded from the receiver and routes the response data to the appropriate internal control logic.

DATA ENCODER: Processes the outgoing audio stream, inserts required synchronization patterns, buffering and routing of the high-bitrate audio data payloads.

DATA TRANSMIT FSM: Manages the primary state machine for the continuous transmission, buffering and routing of the high-bitrate audio data payloads.

PRESCALAR: Divides the system clock based on a configurable prescaler value to derive the necessary serial clocks for both audio data and common data.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesClock Frequency
TSMC 28nm4.5315K100MHz
SMIC 40nm4.8165K100MHz
UMC 55nm8.0655K100MHz

FPGA Device and FamilyLogic ResourcesClock Frequency
AMD VCU118 Virtex Ultrascale+ xcvu9p-flga2104-2L-e755 LUT's100MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.