CORE: Core module interconnects all the sub-modules in the Ethernet AVB MAC IP. Ports of core module are the top level ports for the Ethernet AVB MAC IP.
1722 TS: It is used to select the input from the different streams of data.
PKT MUX: It is used to select either 1722 TS output or DMA output based on the configuration.
PKT CLASSIFIER: It is used to forward the receive output either 1722 TS or DMA module based on the configuration.
TSA: TSA selects algorithm between strict priority, credit based and gate based scheduling based on Transmission Selection Algorithm.
STRICT PRIORITY: It schedules frame in the descending order of the queue. If it has 8 queues then 8th queue is high priority queue.
CREDIT SHAPER: It schedules frames based on the descending order of the queue. Credit will be updated for each queue based on the transmission oppurtunity define with repect of it's credits.
SCHEDULER: Based on the algorithm selected strict or credit based shaper and if scheduler is enabled , scheduler maps the queue selected to the gate module.
GATE: Based on the gate state, it is responsible for forwarding the scheduled frame to MAC which is scheduled by either strict or credit based shaper.
TX FSM: The transmit FSM receives the data from MAC client and maps them to the MAC 1G Interface by encapsulating the Ethernet packet and frame headers.
TX CTRL: Transmit Control block processes the data from system interface/AXI-interfaces and push the data into Transmit FIFO.
TX ASYNC FIFO: TX ASYNC FIFO module stores Tx data and process the data with the different read and write clock domain. Here we have separate tx fifo queue for store the preemptable fram and express frame.
TX ARBITER: It Arbits the Ethernet frames with and without PTP messages based on the availability.
TX MUX: TX MUX is used to transmit the Ethernet frames with and without PTP messages based on TX arbiter.
RX FSM: The Receive FSM receives the data from underlying physical layer and sends them to MAC client by decapsulating the Ethernet Packet headers.
RX CTRL : RX Control block processes the data from MAC 1G interface and push the data into Rx ASYNC FIFO.
RX ASYNC FIFO: RX ASYNC FIFO module stores Tx data and process the data with the different read and write clock domain.
FRAME DECODER: Block to decode frames into respective queues.
FLOW CTRL: Initiating the Transmission of pause frame based on the Receive FIFO's threshold or External requests.
PAUSE TIMER: Implements the Pause timer logic based on the Pause Quanta Value.
BACKOFF: This block contains the time limit for which Tx MAC waits before subsequent retransmission in case of collision in Half Duplex Module.
PTP: It synchronizes itself to the best time source in the network or synchronizes other nodes.This synchronized time is then used by the scheduler to divide the time into cycles and generate phases for different priorities.
PTP CONTROL: PTP control the Transmit MAC to initiate Delay Response message with the timestamp on which Delay Request message was received by MAC.
PTP ENCODER: The PTP Encoder generate PTP Request/Response messages based on the reception of respecitve messages such as Sync/follow up.
PTP DECODER: PTP Decoder process the PTP frames based on type length field matches with PTP type (16’h88F7).
PTP ASYNC FIFO: The PTP frame Transmit FIFO module gets the data from the TX_CTRL module and Transmit to Tx Arbiter.
RTC: Real time counter works by increment the nanoseconds and seconds counter acccording to the time period.
TX TIMESTAMP UNIT: This module captures the time from the counters when any of the PTP event or general messages transmit from MAC TX.
RX TIMESTAMP UNIT: This module captures the time from the counters when any of the PTP event or general messages Received at the MAC RX
MDIO: The management interface is a simple, two-wire, serial interface to connect a management entity and a managed PHY for the purposes of controlling the PHY and gathering status from the PHY.
PRESCALER: The Prescaler block generated management data clock based on which data will be driven on the MDIO bi-directional data bus.
CSR: CSR module has all the configurable registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.
