Laghu-V2 Small RISC-V CPU

Agile 32-bit Embedded Controller

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech Laghu-V2 Small RISC-V CPU is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Versatile processor cores designed for everything from ultra-compact IoT sensors to high-performance edge computing. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

High-Efficiency Pipeline: Advanced multi-stage pipelines optimized for maximum performance-per-watt, outpacing standard legacy architectures.

Scalable ISA: Full support for industry-standard instruction sets (8051, RISC-V) with modular extensions for floating-point, vectors, and security.

Functional Safety (ISO 26262): Available with ASIL-D ready features including hardware redundancy (DMR/TMR) and comprehensive fault-injection testing.

Advanced Debug & Trace: Integrated on-chip debugging solutions compatible with industry-standard development tools for rapid software bring-up.

FEATURES

Compliant with RISC-V RV32IMAC instruction set extensions.
Balanced 3-stage pipeline for high clock frequency and IPC.
Supports Machine and User privilege modes for secure RTOS execution.
Integrated hardware Multiplier and Divider (M-extension).
Full support for Compressed (C) instructions and Atomic (A) operations.
Configurable tightly coupled memories (TCM) for deterministic response.
Standard AHB-Lite or AXI4-Lite system interfaces.
Comprehensive JTAG-based debug support (RISC-V Debug Spec compliant).

FUNCTIONAL DESCRIPTION

ASIC AND FPGA IMPLEMENTATION

Process Node	Frequency (MHz)	Power (uW/MHz)
28nm HPC+	800	< 15
7nm FinFET	1200	< 8
Artix-7 FPGA	250	1.2 DMIPS/MHz

LICENSING OPTIONS

Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.

DELIVERABLES

Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.