Serial Flash Controller IIP

• Compliant with Flash Devices from major Flash Device Vendors
• Full Flash with SPI Master Functionality
• Supports 3 modes of operation
• ->Slave Mode - Accessing flash device through CSR registers from SoC Slave interface
• ->XIP Mode - eXecute In-Place, where core allows direct access to flash memory from SoC Slave interface
• ->HCI Mode - Descriptor based DMA type access from SoC Master Interface
• Supports xSPI (JEDEC’s JESD251), Xccela and Optional Hyperbus standard
• Supports 3 wire and 4 wire operation
• Supports DDR mode of operation
• Single, dual, quad and octal serial data lines
• In built DMA (Host Controller Interface) controller
• Boot image copy Support after power on reset
• Up to 16 slaves supported under master control
• Mode fault error flag with CPU interrupt capability
• Serial clock with programmable polarity and phase
• LSB or MSB mode
• Supports flexible Serial clock generation
• Full duplex and half duplex operation
• Supports any kind of SPI transactions to access any kind of SPI slave device
• Thresholds to generate interrupt
• Software and Hardware Reset
• Control and Status Registers to configure the module
• Configurable Transmit/Receive Data FIFO
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Simple host interfaces enable straightforward integration with microcontrollers and application processors

CORE: Core Module interconnects all the sub-modules in the SPI IP. Ports of core module are the top level ports for the SPI IP.

PRESCALER: Prescaler Module is used to divide the system clock based on the given prescaler value to drive the serial clock input for SPI.

FSM: FSM Module generates the SPI transcations on SPI Master based on commands from CSR block. This blocks implements all the features of SPI specifications.

ARB: ARB Module implements the arbiter to arbit between HCI and FSM access to CSR block.

HCI: HCI Module implements SPI Host controller FSM. The HCI FSM fetches the data from descriptor memory like SPI commands and transmit data bytes and it loads sampled read data bytes into descriptor memory.

XIP: XIP Module implements XIP/AIP mode operation with zero software overhead. XIP Module consists of functionality of both XIP and AIP mode. In XIP (Xecute In Place mode) executing the code directly from the serial flash memory .It will directly read from the Flash memory.In AIP (Access In Place) mode has both read and write operation will execute.It will write data into the flash device.XIP module is connected with soc Slave interface.

BOOT: Boot Module allows the host to read the data from the flash device after the power is on or after the hardware reset is done. It reads the data from the flash device without read command and address

CSR: CSR Module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

• Single Site license for regional development teams.
• Multi-Site license for global corporate deployments.
• Single Design license for specific project cost-efficiency.
• Unlimited Design license for high-volume product roadmaps.

• Complete Verilog/VHDL/SystemC Source Code.
• UVM-compliant verification environment with a comprehensive test suite.
• Production-ready synthesis, Lint, and CDC scripts.
• IP-XACT RDL generated address maps.
• Standard-compliant firmware and Linux/C driver packages.
• Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.