Skip to main content
REQUEST INFO
Skip to main content

SLVS-EC Receiver IIP

Scalable Low Volatage Signaling - Embedded Clock Receiver IIP

SLVS-EC Receiver IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech SLVS-EC Receiver IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Production Proven: Validated in silicon and FPGA across diverse applications.

Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.

Expert Support: Direct access to senior design engineers for rapid integration assistance.

Flexible Deliverables: Available as synthesizable source code or optimized netlists.

FEATURES
  • SLVS-EC Receiver v3.1
  • Fully compliant with the SLVS-EC v3.1 specification and ensures standard-adherent operation across all supported configurations.
  • Backward compatible with v3.0/v2.0/v1.0.
  • Dynamically supports lane configurations of 1, 2, 4, 6 and 8.
  • Supports baud grades up 1152 Mbps to 12500 Mbps.
  • Supports configurable output pixel processing of 1, 2, 4, 8, 16 and 32 pixels per clock.
  • Supports multiple system topologies between CIS and DSP:
    • Basic Topology
    • Multiple I/F Topology
    • Multiple CIS Topology
  • Supports with the RAW pixel data formats of 8, 10, 12, 14 and 16.
  • Dynamically supports Lane Deskew.
  • Supports Embedded data transfer.
  • Compatible with Multiple stream transfer.
  • Supports detecting and reporting the following errors:
    • Invalid control character error
    • Disparity error
    • Line Boundary Error
  • Performs 10b/8b or GCC Symbol Decoding.
  • Supports Error Correction Codes(ECC),Forward Error correction(FEC) and Cyclic redundancy checks(CRC).
  • Fully synthesizable.
  • Static synchronous design.
  • Positive edge clocking and no internal tri-states.
  • Scan test ready.
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors.
FUNCTIONAL DESCRIPTION

CSR: Contains all configuration registers used to monitor status and control the RTL functionality.

LOGICAL PHY: Decodes received PHY control codes and performs either 10b/8b or GCC decoding.

GEARBOX: Converts the 80bit parallel lane input into a constant 136-bit output data stream.

DESKEW: Removes skew between the incoming data laness to ensure proper alignment prior to merging.

GCC LANE: Implements the Channel decoding function by converting channel-coded symbols into decoded data and control symbols.

LANE: Performs comma detection, symbol alignment and initial data decoding on each individual lane.

LANE MERGER: Merges the decoded data from multiple parallel lanes into a single data stream based on the lane configuration.

LINK FSM: Cycles through a series of states to manage the incoming data from the sensor.

BYTE TO PIXEL CONVERTER: Converts the merged incoming byte stream into a standard pixel data based on the configured bits-per-pixel.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesSystem Clock FrequencyVideo Clock FrequencyByte Clock FrequencySerdes Clock Frequency
TSMC 28nm492.72K100MHz148.5MHz62.5MHz62.5MHz
SMIC 40nm542.12K100MHz148.5MHz62.5MHz62.5MHz
UMC 55nm864.11K100MHz148.5MHz62.5MHz62.5MHz

FPGA Device and FamilyLogic ResourcesSystem Clock FrequencyVideo Clock FrequencyByte Clock FrequencySerdes Clock Frequency
AMD-xcvu9p-flga2104-2L-e90353 LUT's100MHz148.5MHz62.5MHz62.5MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.