USB2.x HOST IIP

• Compliant with USB 2.0 specification.
• Compliant to EHCI Specification Rev 1.0
• Compliant to xHCI Specification Rev 1.2
• Supports configurable USB Speeds – HS/FS/LS
• Software configurable Supports UTMI Parallel and serial mode.
• USB2 PHY Interface: 8/16 bits UTMI plus level 3
• Supports UTMI transceivers. Operates at High-speed (480 Mbps), Full-speed (12Mbps) and Low-speed (1.5 Mbps).
• Enumeration of low-speed, full-speed, and high-speed devices.
• Supports Interrupt/Bulk/Isochronous/Control Transfers.
• Supports High Bandwidth Interrupt and Isochronous endpoints.
• CRC5 generation and checking for Tokens.
• CRC16 checking and generation for HS/FS/LS data packets.
• Control transfers supported by Endpoint 0
• Supports configurable internal buffers and Protocol Layer Error Handling.
• Separate round robin scheduling algorithm within Periodic and Non-periodic endpoints pipes.
• Supports maximum payload size for each endpoint.
• Supports USB Suspend state and supports remote wakeup devices.
• Supports all HS/FS USB Link Power Management States – L1, L2.
• Implements all the EHCI and xHCI compliant registers.
• Proprietary DMA engine for initiating/completing USB transactions limiting software overhead. Can be used with Host mode operation.
• Fully synthesizable.
• Static synchronous design.
• Positive edge clocking and no internal tri-states.
• Scan test ready.
• Simple host interfaces enable straightforward integration with microcontrollers and application processors. Available as Additional Feature at extra cost
• ISO26262 Functional safety(ASIL B/D)
• ISO26262 Safety Manual (SAM) Document
• ISO26262 Failure Modes, Effects and Diagnostics Analysis (FMEDA) Document
• Memories with ECC
• Basic Firmware - Linux Driver
• XML Support
• Customer SoC I/F

CORE: Core module interconnects all the sub-modules in the USB2_HOST IP. Ports of core module are the top level ports for the USB2_HOST IP.

USB TRANSACTOR: USB transactor module implements the logic for transmitting and receiving High, Full and Low speed packets and manages various USB bus conditions.

TRANSACTION SCHEDULER: Transaction Scheduler module schedule the transfer based on the endpoint type and pushes the device and endpoint address in periodic and non-periodic scheduling pipe and managing the endpoint and device contexts and Maintaining the dequeue pointer and data buffer pointer for each and every endpoint.

COMMAND PROCESSOR: Command processor module fetches the command TRB from command ring and decode and process it and update the device contexts based on the command operation and generates the event trb for the command and sends it to the event ring controller block.

EVENT RING CONTROLLER: Event ring Controller module manages event ring FULL and empty condition checking and generating event ring full event and interrupt based on the event ring empty condition, interrupt moderation, interrupt interval counter.

CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

• Single Site license for regional development teams.
• Multi-Site license for global corporate deployments.
• Single Design license for specific project cost-efficiency.
• Unlimited Design license for high-volume product roadmaps.

• Complete Verilog/VHDL/SystemC Source Code.
• UVM-compliant verification environment with a comprehensive test suite.
• Production-ready synthesis, Lint, and CDC scripts.
• IP-XACT RDL generated address maps.
• Standard-compliant firmware and Linux/C driver packages.
• Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.