MIPI SPMI Slave AXI Bridge IIP

• Supports 2.0 and 1.0 MIPI SPMI Specification
• Full MIPI SPMI Slave functionality
• Allows external devices to access the internal AXI Bus
• Supports following frames
• Command Frame
• Data/Address Frame
• No Response Frame
• Supports ACK/NACK as per 2.0 specs
• Support for slave requests through Alert(A)/Slave Request(SR) bit.
• Support for slave request hold.
• Glitch suppression (optional).
• Supports extended register read/writes
• Supports wakeup command
• Supports Authentication Command Sequence
• Device Descriptor Block command Sequences
• Supports AXI Master Read/ Write capability
• Supports AXI Slave
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Simple host interfaces enable straightforward integration with micro-controllers and application processors
• This core achieves ASIL B and can be made to achieve ASIL D as per ISO26262

CORE: Core module interconnects all the sub-modules in the SPMI SLAVE AXI BRIDGE IIP. Ports of core module are the top level ports for Slave AXI BRIDGE IIP

• Logic for SDA output enable (o_sda_en)
• Reset generation

FSM: FSM module process SPMI commands once SSC is detected.FSM responds to SPMI commands (ACK/NACK for Write transfer and Read data for read transfer) only if Slave ID is matched with the ID driven on the SPMI bus by the Master/RCS,else FSM silently trace SPMI transaction.

REQ: Request FSM process the RCS pending transaction.Request FSM drives its own Slave ID during Slave arbitration phase either with priority ‘A’ bit or ‘SR’ bit.If it wins the arbitration,it processes the pending transfer once SSC detects.It comprises of two procedural blocks.One block monitors the Arbitration phase and the other processes the Pending transfer if RCS wins the arbitration.

CSR: CSR module has all the configuration registers of Slave IP,Interrupt status registers and RCS State Machine.Also it has the logic to run TBT timer.

START: Start module detects the SSC and arbitration start condition on SPMI bus. Start detect and arbitration start signals from this module triggers Slave FSM, REQ FSM and RCS FSM (arbitration handling) to process a SPMI transaction.

SDA_OUT: SDA OUT module is to enable / disable SDA driver based on the signals from FSM, Request FSM and CSR Module. It is the block where value onto Slave’s SDA bus is loaded as per the value provided through the ports from FSM, Request FSM and CSR Module.

AXI Slave: The AXI Slave as external interface helps to write or read control and status register in CSR module. The SoC Slave ports connect CSR and AXI Slave Module.

AXI Master: AXI master reads the write commands from SPMI slave command and generates the AXI write transactions on AXI bus. Similarly it reads the read commands from SPMI slave and converts into AXI reads transactions.

• Single Site license for regional development teams.
• Multi-Site license for global corporate deployments.
• Single Design license for specific project cost-efficiency.
• Unlimited Design license for high-volume product roadmaps.

• Complete Verilog/VHDL/SystemC Source Code.
• UVM-compliant verification environment with a comprehensive test suite.
• Production-ready synthesis, Lint, and CDC scripts.
• IP-XACT RDL generated address maps.
• Standard-compliant firmware and Linux/C driver packages.
• Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.