ETHERNET 2.5G PCS IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech ETHERNET 2.5G PCS IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Designed for data center, enterprise networking, and industrial automation environments. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Low Latency Architecture: Engineered for real-time applications with deterministic latency, ideal for TSN (Time Sensitive Networking).

Scalable Performance: Seamless migration paths from 10M to 800G, supporting a wide range of networking requirements.

Robust Compliance: Fully compliant with IEEE 802.3 standards, ensuring interoperability with standard network equipment.

Integrated Offload: Advanced TCP/UDP offload engines (TOE) to reduce host processor overhead.

FEATURES

Supports IEEE Standard 802cb.3.2018 Clause 127 for 2.5G PCS
Supports TBI Interface
Supports 2.5Gbps
Supports GPII Interface (Gbps PCS Internal Interface)
Supports 8b/10b encoding to generate code groups in transmit path
Supports 10b/8b decoding to convert received code groups to 32 XGMII data bits and 4 XGMII control bits
Supports synchronization of code groups to determine code group boundaries
Supports IEEE Standard 802.3.2022 Clause 37 Auto negotiation and Clause 73 BP Auto negotiation
Supports Loopback Functionality
Supports link fault and error indications
Supports IEEE Standard 802.3az Energy Efficient Ethernet.
Supports Configurable Management Interface (MDIO / SoC Bus)
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors

FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the ETHERNET PCS 2.5G IP. Ports of core module are the top level ports for the ETHERNET PCS 2.5G IP.

WORD ENCODE: WORD ENCODE module maps the four XGMII lanes onto four 2.5GPII symbols, and their associated transmit enable and transmit error bits.

TX DATA RATE ADAPTATION: TX Data Rate Adaptation module receives data from MAC via XGMII Interface.

TX FSM: TX FSM module is used to implement both encapsulation and 8B/10B encoding of the GMII data.

ENC_8B_10B: To attain DC balance and for clock recovery,ENC8_8B_10B module is used for encoding the eight bit data into more transition ten bit code groups.

TX LPI TIMER: TX LPI Timer module implements the LPI sleep, quiet and refresh timers when LPI is asserted.

SYNC FSM: SYNC FSM module is used to synchronize the 10bit block from the incoming code group based on the Comma Detect.

RX FSM: RX FSM module is used to maps the 8bit data with the GMII signals.

RX DATA RATE ADAPTATION: RX Rate Adaptation module adapts the data rates for received data.

DEC_8B_10B: DEC 8B/10B module is used for decoding the ten bit code groups into eight bit data once synchronization lock is attained.

RX LPI TIMER: RX LPI Timer module implements the LPI quiet, wake and wake fault timers with the LPI reception.

COMMA DETECT: COMMA DETECT module is used to detect the valid code group on the receive PCS for acquiring alignment with the byte boundary.

WORD DECODE: The Word Decode process maps the four 2.5GPII symbols onto the four XGMII lanes MAC Interface.

CSR: CSR module has Control Status registers that controls the IP. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

ASIC AND FPGA IMPLEMENTATION

ASIC Technology	Logic Resources	Clock Frequency	MAC Clock Frequency	Serdes Clock Frequency	XGMII Clock Frequency
TSMC 28nm	186.13K	167MHz	125MHz	125MHz	125MHz
UMSC 55nm	213.13K	167MHz	125MHz	125MHz	125MHz
SMIC 40nm	198.13K	167MHz	125MHz	125MHz	125MHz

FPGA Device and Family	Logic Resources	Clock Frequency	MAC Clock Frequency	Serdes Clock Frequency	XGMII Clock Frequency
Kintex 7,31022 LUT's	167MHz	125MHz	125MHz	125MHz

LICENSING OPTIONS

Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.

DELIVERABLES

Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.