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SAS Target IIP

SAS Target IIP

Overview

It supports all three modes of data transfer:

COMPETITIVE ADVANTAGE

The SivaKali Tech SAS Target IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Production Proven: Validated in silicon and FPGA across diverse applications.

Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.

Expert Support: Direct access to senior design engineers for rapid integration assistance.

Flexible Deliverables: Available as synthesizable source code or optimized netlists.

FEATURES
  • Supports SPL 1.0/2.0/3.0/4.0/5.0 Specs
  • Supports SAS 1.5,3,6,12 and 22.5 Gbps data transfer rates
  • Supports SATA 1.5,3 and 6 Gbps data transfer rates
  • Supports native 32bit PHY Interface
  • Supports 8b/10b Encoding
  • Supports 10 bit, 20 bit ,40 bit parallel interface
  • Supports Narrow ports and wide ports
  • Supports Identify and Reset sequences
  • Supports Link sequences
  • Supports SSP , SMP and STP protocols
  • Supports Physical link rate tolerance management
  • Supports STP, SSP & SMP Link layer Connections
  • Selectable Primitive CONT and fill substitution processing
  • Supports STP & SSP flow control
  • Supports Dword Byte order. Supports Discover process
  • Complete Disparity checking
  • Supports BMC Encoding
  • Supports SNW-3 phy capabilities bits
  • Supports Spread Spectrum Clocking Modulation techniques
  • Complete Kcode & Dcode validity and alignment
  • Complete 8b/10b Encode and Decode functions
  • Supports OOB sequence generation and checking
  • Supports Successful low phy power conditions handshake sequence
  • Supports SAS Dword mode and Packet mode
  • Supports Forward error correction encoding & decoding
  • Supports Interleaved SPL Packet mode encoding & decoding
  • Complete dword synchronization,SPL packet synchronization
  • Supports SAS speed negotiation sequence
  • Supports Train_Tx-SNW & Train_Rx-SNW for SAS Dword mode and Packet mode
  • Supports primitive encoding, binary primitive coding, and extended binary primitive coding
  • Resynchronization phy layer state machines
  • Supports Bit order of CRC and scrambler for SAS Dword mode and Packet mode
  • Supports SSP frame fields
  • Supports STP frame fields
  • Supports SMP frame fields
  • Supports standard SCSI, SMP and STP commands
  • Complete overall control and phy control state machine
  • Supports link layer Rate matching for SAS Dword mode and Packet mode
  • Supports Address frames
  • Supports all PHY power conditions and management
  • Supports DMA and PIO commands
  • Device Signature returns Feature
  • Supports SATA features
  • Implements the shadow register block and the serial ATA status and control registers
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the SAS Target IP. Ports of core module are the top level ports for the SAS Target IP.

CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

SSP_APPS,SMP_APPS,STP_APPS : Based on the command, application layer will generate the command and made request to transport layer for FIS generation and responses for all three modes.

STP_PORT_CONTROL: Resposible to request the port layer to open the connection in the available phy when STP transport layer is having pending tx frame. It always collects the OA frame credentias like destination address and others from CSR module.

S_PORT: Interaction with port layer and SL PHY state machines. It gets the frame transmission request from the Port Layer Over all control state machine.

POWER_CONTROL : Controls the power mechanisms of SAS device.

DMA PORT : This module is used to transfer the data from system memory to Hard disk drive or writing the data to system memory when device Hard disk drive sends data in response with read command.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesSystem Clock FrequencyLink Clock FrequencySerdes Clock FrequencyMaster Clock Frequency
TSMC 28nm178k100MHZ6MHZ150MHZ100MHZ
UMSC 55nm257k100MHZ6MHZ150MHZ100MHZ
SMIC 40nm213k100MHZ6MHZ150MHZ100MHZ

FPGA Device and FamilyLogic ResourcesSystem Clock FrequencyLink Clock FrequencySerdes Clock FrequencyMaster Clock Frequency
Virtex-7 VC70729666 LUT's100MHZ6MHZ150MHZ100MHZ

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.