Pulse Density Modulation 2 Pulse Code Modulation IIP
Overview
COMPETITIVE ADVANTAGE
The SivaKali Tech PDM2PCM IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.
COMPETITIVE ADVANTAGE
Production Proven: Validated in silicon and FPGA across diverse applications.
Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.
Expert Support: Direct access to senior design engineers for rapid integration assistance.
Flexible Deliverables: Available as synthesizable source code or optimized netlists.
FEATURES
Pulse Density Modulation 2 Pulse Code Modulation IIP
Provides full Pulse Density Modulation (PDM) to Pulse Code Modulation (PCM) conversion.
Supports mono and optional stereo mode operations.
Configurable PDM microphone clock frequency.
Compatible with a comprehensive range of variable sampling frequencies:
Low/Standard rates (8KHz, 16KHz, 22.05KHz, and 32KHz)
High-Fidelity rates (44.1KHz, 48KHz, 88.2KHz, and 96KHz)
High Resolution rates (176.4 and 192KHz)
Accepts a 1-bit PDM input stream and generates configurable 16, 20 and 24 bit PCM digital data outputs.
Supports programmable decimation ratios of 24X, 32X, 48X and 64X.
Programmable gain control ranging from -12dB to +12dB.
Supports variable gain control values:
-12dB
-6dB
-3dB
0dB
+2dB
+3dB
+6dB
+12dB
Includes optional high pass filters to eliminate DC offset and low frequency noise.
Integrates a robust hardware FIFO depth of 255 elements where each element is 24-bit wide.
Interrupt support to notify when specific events or error occur.
Additional interrupts for FIFO underflow and overflow with separate enables.
Fully synthesizable.
Static synchronous design.
Positive edge clocking and no internal tri-states.
Scan test ready.
Simple host interfaces enable straightforward integration with microcontrollers and application processors.
FUNCTIONAL DESCRIPTION
CSR: Contains all configuration registers used to monitor status and control the RTL functionality.
CIC: Integrates and decimates the high rate PDM input stream to generate a lower rate PCM signal. The internal comb stage removes out of band spectral noise to produce a clean based audio output.
LPF: Removes high frequency noise and allows a only low frequency signals to pass, ensuring a smooth anti aliased and clean PCM output.
HPF: Removes unwanted low frequency components and allows only higher frequency signals to pass isolating the desired audio spectrum.
FIR: Uses fixed coefficients to shape the input signal providing digital frequency filtering while maintaining a strictly linear phase output.
GAIN: Dynamically adjusts the amplitude of the digital audio signals increasing or decreasing its strength to control signal level for proper downstream processing or final output.
ASIC AND FPGA IMPLEMENTATION
ASIC Technology
Logic Resources
System Clock Frequency
PDM Clock Frequency
TSMC 28nm
41.92K
50MHz
3.072MHz
SMIC 40nm
43.22K
50MHz
3.072MHz
UMC 55nm
84.85K
50MHz
3.072MHz
FPGA Device and Family
Logic Resources
System Clock Frequency
PDM Clock Frequency
AMD-xcvu9p-flga2104-2L-e
7203 LUT's
50MHz
3.072MHz
LICENSING OPTIONS
Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.
