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MIPI CSI-2 Transmitter IIP

MIPI Camera Serial Interface Transmitter IIP

MIPI CSI-2 Transmitter IIP

Overview

1.Control and synchronization mode

2.High-speed data transmission mode

COMPETITIVE ADVANTAGE

The SivaKali Tech MIPI CSI-2 Transmitter IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Ideal for mobile, automotive, and IoT applications requiring high-bandwidth camera and display interfaces. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Low Power & High Efficiency: Optimized for mobile and battery-operated devices with advanced power gating and low-leakage architecture.

Silicon Proven: Validated on leading foundry nodes (5nm, 7nm, 12nm, 28nm), ensuring reduced integration risk.

Comprehensive Support: Full compliance with latest MIPI Alliance specifications, including CSI-2, DSI-2, and I3C.

Flexible Licensing: Cost-effective, royalty-free licensing models compared to restrictive tier-1 vendor options.

FEATURES
  • MIPI-CSI2 v4.1 Transmitter
  • Fully compliant with the MIPI_CSI2 v4.1 specification and ensures standard-adherent operation across all supported configurations
  • Supports full MIPI CSI-2 functionality with DPHY v3.5.
    • Dynamically supports lane configurations upto 8 lanes
    • Support data rate ranges from 80Mbps to 9Gbps.
    • Supports programmable parallel interface widths of 8bits, 16bits and 32bits
    • Supports 16 interleaved Virtual channel.
  • Supports full MIPI CSI-2 functionality with CPHY v3.0.
    • Dynamically supports lane configurations upto 8 lanes
    • Support data rate ranges from 0.08Gsps to 6Gsps.
    • Supports programmable parallel interface widths of 16bits, 32bits and 64bits
    • Supports 32 interleaved Virtual channel.
    • Supports CPHY Calibration Preamble.
  • Supports configurable input pixel processing of 2 pixels per clock
  • Supports maximum resolution up to 8k@60Hz
  • Compatible with the video formats which are mentioned in MIPI_CSI2 v4.1
    • RGB 5:6:5 (16 Bits Per Pixel)
    • RGB 4:4:4 (12,15,18,24 Bits Per Pixel)
    • LYUV 4:2:0 (8 Bits Per Pixel)
    • YUV 4:2:0 (8,10 Bits Per Pixel)
    • YUV 4:2:2 (8,10 Bits Per Pixel)
    • RAW (6,7,8,10,12,14,16,20,24,28 Bits Per Pixel)
  • Supports upto 8 User defined datatypes.
  • Integrates Error Correction Codes(ECC) and Cyclic redundancy checks(CRC)
  • Compliant Alternative low power mode and Escape Mode
  • Compliant with Bi-directional communication.
  • Compliant with Data Scrambler.
  • Compliant with Latency Reduction and Transport Efficiency (LRTE)
  • Compliant with Unified Serial Link (USL)
  • Compliant with Smart Region of Interest (SROI)
  • Compliant with Always-On Sentinel Conduit (AOSC)
  • Fully synthesizable.
  • Static synchronous design.
  • Positive edge clocking and no internal tri-states.
  • Scan test ready.
  • Simple interface allows easy connection to microprocessor/microcontroller device.
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the MIPI_CSI2 TX IP. Ports of core module are the top level ports for the MIPI_CSI2 TX IP.

CAMERA INTERFACE CONTROL : Camera Interface Control module collect video from data interface and control the data transmission.

CAMERA INTERFACE : Camera Interface module is used to converts the pixel data into byte data.

DPCM ENCODER : DPCM Encoder module is used to encode the input data.

DPCM DECODER : DPCM Decode module is used to decode the data present.

PACKETISER : Packetiser module is used to packetise the input data based on the packet structure.

LANE DISTRIBUTION : Lane Distribution module is used to send the data based on the number of lanes.

CSR: CSR module stores configurable registers and drives outputs based on their functionality.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesSystem Clock FrequencyLane Clock FrequencyPixel Clock Frequency
TSMC 28nm114.50K50MHz182.25MHz63.75MHz
UMSC 55nm118.81K50MHz182.25MHz63.75MHz
SMIC 40nm197.21K50MHz182.25MHz63.75MHz

FPGA Device and FamilyLogic ResourcesClock Frequency
AMD-xcvu9p-flga2104-2L-e19083.33 LUT's50MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.