CHI to UCIe Bridge IIP

• Supports specification version 1.0, 1.1, 2.0 and 3.0
• Supported Mode - Endpoint, Root Complex
• Supported Package - Standard package, Advanced Package
• Supported Protocol - CHI
• Supported Flit Formats
• Raw Format
• 68B Flit Format
• Standard 256B End Header Flit Format
• Standard 256B Start Header Flit Format
• Latency-Optimized 256B without Optional Bytes Flit Format
• Latency-Optimized 256B with Optional Bytes Flit Format
• Supports 4 GT/s, 8 GT/s, 12 GT/s, 16 GT/s, 24 GT/s, 32 GT/s, 48 GT/s and 64 GT/s speeds with:
  • 500 MHz, 1 GHz, 1.5 GHz, 2 GHz, 3 GHz, 4 GHz, 6GHz and 8GHz UCIe clock frequency
• Supports 800 MHZ speed for sideband data
• Supports 16 Lanes, 32 Lanes and 64 Lanes
• Supports Sideband messaging for link training and parameter exchange
• Supports Sideband Mailbox Mechanism for read and write configuration
• Supports Clock gating Mechanism
• Supports all handshake mechanism
• Supports Data Link Feature Exchange
• Supports Link Power Management
• Supports Multi Stack protocol
• Supports all Vendor defined Sideband messages
• Supports UCIe Retimers
• Supports Flit Retry Mechanism
• Supports Flits CRC
• Compliant with the latest ARM AMBA5 CHI specification (CHI-D)
• Support for Protocol, Network and Link layer communication, including flow control mechanisms across RN2HN and HN2SN links
• Supports all CHI protocol node types:
  • Request Nodes (RN-F, RN-D and RN-I)
  • Home Nodes (HN-F, HN-I and MN)
  • Slave Nodes (SN-F and SN-I)
• Support for skipping link initialization and retrying failed link initialization
• Configurable credit including dynamic and pre-allocated credit control
• Cache model support in Master and Interconnect (programmable). Monitor has backdoor access to these cache models
• Supports Speculative read and Snoop filtering
• Supports all Transaction types and Opcodes
• Supports Direct Memory Transfer and Direct Cache Transfer
• Supports Exclusive accesses, Cache Stashing, DVM Operations
• Supports Deallocating transactions, Poison and Data Check
• Supports all ARM AMBA5 CHI data widths
• Support for Request transactions with/without a Retry and cancelling of transactions
• Ability to issue multiple outstanding Non-snoopable/Snoopable transactions
• Programmable Protocol flit delays and different channels delays. Interconnect has the ability to replicate RN/SN inserted delays
• Supports all write/read responses and snoop responses
• Fine grain control of below:
  • Requester transaction including main memory access
  • Completer response to a Requester transaction and Requester
  • Acknowledgment/response to Completer's response
  • Interconnect generated snoop transaction to Snooped RNs
  • Interconnect generated main memory access transactions
  • Snooped RN response to a snoop transaction
• Supports fine grain control of response per address or per transaction
• Device and Normal memory types support
• Support for ordering of transactions/responses and reordering of data packets
• Support for error injection during Link initialization
• Ability to inject errors during transfers
• Supports constrained randomization of protocol attributes
• Programmable Timeout insertion
• Supports FIFO memory
• Rich set of configuration parameters to control CHI5 functionality
• Supports Positive edge clocking and no internal tri-states
• Scan test ready
• Fully synthesizable
• Static synchronous design
• Simple interface allows easy connection to microprocessor/ microcontroller devices

CORE: Core module interconnects all the sub-modules and provides the top level ports for the entire CHI to UCIe Bridge IP.

CSR: CSR module has all the registers. It decodes configuration data and assigns it to specific ports to drive the IP's functionality.

ATU: Address translation unit module translates the UCIe address to csr address.

PROTOCOL LAYER: The protocol layer performs APB-to-UCIe bridge to transfer sideband data using UCIe sideband packet formats and the CHI UCIe bridge manages high-speed data communication by converting CHI transactions into UCIe mainband flits and reconstructing them on reception.

D2D ADAPTER: The D2D Adapter module manages both sideband and mainband communication by packing, and unpacking sideband packets, while packaging protocol data into protected flits for reliable high-speed transfer between local and remote dies.

• Single Site license for regional development teams.
• Multi-Site license for global corporate deployments.
• Single Design license for specific project cost-efficiency.
• Unlimited Design license for high-volume product roadmaps.

• Complete Verilog/VHDL/SystemC Source Code.
• UVM-compliant verification environment with a comprehensive test suite.
• Production-ready synthesis, Lint, and CDC scripts.
• IP-XACT RDL generated address maps.
• Standard-compliant firmware and Linux/C driver packages.
• Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.