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CAN FD LIGHT Controller IIP

CAN FD LIGHT Controller IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech CAN FD LIGHT Controller IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Engineered for ADAS, infotainment, and vehicle control units (ECUs). Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Automotive Grade: Developed with ISO 26262 functional safety processes (ASIL-B/D Ready).

High Reliability: Robust error handling and fault tolerance for mission-critical vehicle networks.

Legacy & Future: Supports both classic protocols and modern, high-speed automotive networking standards.

Cost Effective: Affordable licensing for high-volume automotive production runs.

FEATURES
  • Supports CAN FD light version 1.0.1 compliant
  • Full CAN FD light transmit and receive functionality
  • Supports bit rate up to 1 Mbps for CAN FD light
  • Supports Data frame and 0 to 64 data bytes
  • Supports 11 bit Identifier
  • Supports all types of error detection
    • Stuff error
    • CRC error
    • Form error
  • Supports programmable clock output
  • Support the 17-bit CRC and 21-bit CRC for DFs
  • Supports message acceptance using single filter and double filter
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to microprocessor/microcontroller devices
  • This core achieves ASIL B and can be made to achieve ASIL D as per ISO26262
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the CAN FD LIGHT Controller IP. Ports of core module are the top level ports for the CAN FD LIGHT Controller IP.

CSR: CSR module has all the Control and status registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality. This block contains interrupt enable and status registers.

TFSM: TFSM Module is responsible for driving CAN FD Light frames through Bus.

RFSM: RFSM Module is responsible for sampling CAN FD Light frames through Bus and also for Error detection.

TIMING: TIMING Module is responsible for Bit timing characteristics of CAN FD Light protocol.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesClock Frequency
TSMC 12nm10.83K20MHz
TSMC 28nm7.45K20MHz
TSMC 90nm10.75K20MHz
TSMC 130nm10.75K20MHz
TSMC 180nm11.44K20MHz
GF 180nm7.84K20MHz
SMIC 40nm7.99K20MHz
UMSC 55nm12.84K20MHz

FPGA Device and FamilyLogic ResourcesClock Frequency
AMD-xcvu9p-flga2104-2L-e1241 LUT's20MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.