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ETHERNET TSA IIP

ETHERNET TSA IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech ETHERNET TSA IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Designed for data center, enterprise networking, and industrial automation environments. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Low Latency Architecture: Engineered for real-time applications with deterministic latency, ideal for TSN (Time Sensitive Networking).

Scalable Performance: Seamless migration paths from 10M to 800G, supporting a wide range of networking requirements.

Robust Compliance: Fully compliant with IEEE 802.3 standards, ensuring interoperability with standard network equipment.

Integrated Offload: Advanced TCP/UDP offload engines (TOE) to reduce host processor overhead.

FEATURES
  • Compliant with IEEE 802.1 Q Standard (IEEE 802.1Qbu)
  • Supports Strict and Credit Based Shaper Algorithm based on the select mode
  • Support for Class based scheduling with 8 traffic classes and an express queue
  • Support initiation of MAC to preempt the frame when an Express traffic is available
  • Support for different modes of operation – Normal and Cut Through
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the Ethernet TSA IP. Ports of core module are the top level ports for the Ethernet TSA IP.

TSA: TSA selects algorithm between strict priority, credit based and gate based scheduling based on Transmission Selection Algorithm.

STRICT PRIORITY: It schedules frame in the descending order of the queue. If it has 8 queues then 8th queue is high priority queue.

CREDIT SHAPER: It schedules frames based on the descending order of the queue. Credit will be updated for each queue based on the transmission oppurtunity define with repect of its credits.

SCHEDULER: Based on the algorithm selected strict or credit based shaper and if scheduler is enabled , scheduler maps the queue selected to the gate module.

GATE: Based on the gate state, it is responsible for forwarding the scheduled frame to MAC which is scheduled by either strict or credit based shaper.

CSR: CSR module has all the configurable registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesClock FrequencyTransmit frequency
TSMC 28nm2.57K125MHz125MHz
UMSC 55nm3.98K125MHz125MHz
SMIC 40nm2.87K125MHz125MHz

FPGA Device and FamilyLogic ResourcesClock FrequencyTransmit frequency
AMD-xcvu9p-flga2104-2L-e428 LUT's125MHz125MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.