The SivaKali Tech SPI Slave IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. The backbone of system control and peripheral connectivity for any SoC. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.
COMPETITIVE ADVANTAGE
Ultra-Low Gate Count: Extremely efficient implementation, negligible impact on total SoC area.
Simple Integration: Standard AMBA (APB/AHB) or AXI-Lite interfaces for plug-and-play system connectivity.
Proven Reliability: Thousands of production deployments ensuring rock-solid stability.
Driver Support: Includes bare-metal and Linux drivers to accelerate software development.
FEATURES
Compliant with SPI Block Guide 4.01 Specification
Full SPI Slave functionality
Supports flexible transfer format to work with slower interfaces
Supports Single, Dual, Quad, Octal data widths
Supports clock less operations
Suitable for lower power operations
Simple command/Address/data format for SPI slave devices
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors
Optionally this core can be built to have I2C interface for application where slave can have multiple interfaces like SPI or I2C Interface
FUNCTIONAL DESCRIPTION
CORE: Core Module interconnects all the sub-modules in the SPI IP. Ports of core module are the top level ports for the SPI IP.
FSM: FSM Module generates the SPI transcations on SPI Master based on commands from CSR block. This blocks implements all the features of SPI specifications.
ARB: Arbiter Module selects the read write operation of DMA and FSM module to access the CSR module.
DMA: DMA Module is used to write/read the data to/from DMA memory through SoC master interface.
CSR: CSR Module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.
ASIC AND FPGA IMPLEMENTATION
ASIC Technology
Logic Resources
System Clock Frequency
DMA Clock Frequency
Serial Clock Frequency
TSMC 12nm
15.40K
100MHz
100MHz
50MHz
TSMC 28nm
10.10K
100MHz
100MHz
50MHz
TSMC 90nm
15.07K
100MHz
100MHz
50MHz
TSMC 130nm
15.07K
100MHz
100MHz
50MHz
TSMC 180nm
15.66K
100MHz
100MHz
50MHz
UMSC 55nm
18.56K
100MHz
100MHz
50MHz
SMIC 40nm
11.10K
100MHz
100MHz
50MHz
GF 180nm
11.15K
100MHZ
100MHZ
50MHZ
FPGA Device and Family
Logic Resources
Clock Frequency
AMD-xcvu9p-flga2104-2L-e
51685 LUT's
100MHz
LICENSING OPTIONS
Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.
