Sony/Philips Digital Interface Format Receiver IIP
Overview
COMPETITIVE ADVANTAGE
The SivaKali Tech SPDIF Receiver IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.
COMPETITIVE ADVANTAGE
Production Proven: Validated in silicon and FPGA across diverse applications.
Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.
Expert Support: Direct access to senior design engineers for rapid integration assistance.
Flexible Deliverables: Available as synthesizable source code or optimized netlists.
FEATURES
SPDIF Receiver IIP
Fully compliant with the IEC 60958 and IEC 61937 specification and ensures standard-adherent operation across all supported configurations.
Compatible with SMPTE 337M standards for non Linear PCM Audio.
Compatible with AES/EBU, AES3 standards for Linear PCM Audio.
Supports 2 audio channels.
Supports variable sampling frequencies:
22.05KHz
24KHz
32 KHz
44.1 KHz
48 KHz
88.2 KHz
96 KHz
176.4 KHz
192 KHz
352.8 KHz
384 KHz
Supports audio bit sample as 16, 17, 18, 19, 20, 21, 22, 23 and 24.
Supports the Biphase-mark coding.
Supports DMA hardware handshake interface.
Interrupt support to notify when specific events or error occur.
Fully synthesizable.
Static synchronous design.
Positive edge clocking and no internal tri-states.
Scan test ready.
Simple host interfaces enable straightforward integration with microcontrollers and application processors.
FUNCTIONAL DESCRIPTION
CSR: Contains all configuration registers used to monitor status and control the RTL functionality.
PRESCALAR: Prescalar module performs clock recovery by extracting and generating the internal bit clock from the incoming SPDIF data stream.
FSM: FSM module synchronizes with SPDIF preambles and reliably extracts audio data and control information from the incoming stream.
ASIC AND FPGA IMPLEMENTATION
ASIC Technology
Logic Resources
System Clock Frequency
SPDIF Clock Frequency
TSMC 28nm
4.45K
100MHz
24.576MHz
SMIC 40nm
4.88K
100MHz
24.576MHz
UMC 55nm
8.34K
100MHz
24.576MHz
FPGA Device and Family
Logic Resources
System Clock Frequency
SPDIF Clock Frequency
AMD-xcvu9p-flga2104-2L-e
813 LUT's
100MHz
24.576MHz
LICENSING OPTIONS
Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.
