Skip to main content
REQUEST INFO
Skip to main content

PCIE CONTROLLER IIP

PCIE CONTROLLER IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech PCIE CONTROLLER IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Enabling next-generation server, storage, and accelerator connectivity. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

High Throughput: Multi-lane architecture supporting maximum theoretical link speeds.

Low Latency: Optimized datapath for minimal latency, crucial for coherent interconnects like CXL and UCIe.

Virtualization Support: Hardware support for SR-IOV to enable efficient resource sharing in virtualized environments.

Reliability features: Advanced RAS (Reliability, Availability, and Serviceability) features for enterprise class stability.

FEATURES
  • Compliant with PCIE 6.x/5.x/4.x/3.x/2.x/1.x Specifications
  • Full PCIE Controller functionality
  • Supports PIPE interface.
  • Supports the following modes:
  • ->Root Complex
  • ->Endpoint
  • Supports full LTSSM state machine
  • Supports Speed and Link Width negotiation
  • Supports lane polarity inversion detection and correction
  • Supports lane reversal detection and correction
  • Supports up configure and lane-to-lane de-skew Supports full link speed and width negotiation up to 16 Lanes
  • Supports Linkwidth negotiation through L0P state in flit mode
  • Supports up to 64 bits pipe width
  • Supports up to 80 bits Serdes width
  • Supports Gray coding and Precoding in Gen 6
  • Supports NRZ scrambling for TS0 order sets in Gen 6
  • Supports Link management DLLPs in flit mode
  • Supports Shared Flow Control and Dedicated flow control in flit mode
  • Supports Configurable Fixed Pclk/Fixed Data path implementation for Speed switching
  • Supports data scrambling for Gen 1,2,3,4,5,6
  • Configurable timers and timeout
  • Supports Lane Margining at Receiver
  • Supports full DL state machines
  • Check all framing, LCRC, and lane rules
  • Check all DLLP fields and formatting
  • Supports Retry Mechanism
  • Supports Scaled Flow Control
  • Supports Data Link Feature Exchange
  • Supports queuing for 8 Virtual Channels with configurable depth
  • Supports up to 8 Traffic Classes
  • Supports multi-function
  • Configurable TC to VC queue mapping
  • Supports MSI/MSI-X Interrupts
  • Multiple Requester / Completer applications, including user supplied applications
  • User interface for direct TLP queuing and receipt
  • Check all TLPs for correct formation of headers, prefixes, and ECRC
  • Supports ASPM and Software controlled Power Management
  • Supports Link Power Management Supports bidirectional open-drain clock request signal
  • Supports L1 PM Sub states
  • Supports up to 14-Bit Tag Requester
  • Supports enhanced Allocation
  • Supports emergency Power Reduction State
  • Supports DMA(optional)
  • Support Flit Mode and Non flit mode based on Datarate
  • Supports Flit CRC and FEC.
  • Supports 40B SKIP
  • Fully synthesizable.
  • Static synchronous design.
  • Positive edge clocking and no internal tri-states.
  • Scan test ready.
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors. Available as Additional Feature at extra cost
  • Support additional functionality of RCB,PME,PTM,DMA,Atomic OP,SR-IOV,TPH,Vendor specific Messages
  • ISO26262 Functional safety(ASIL-B/D)
    • ISO26262 Safety Manual (SAM) Document
    • ISO26262 Failure Modes, Effects and Diagnostics Analysis(FMEDA) Document
  • Memories with ECC
  • Customized SoC I/F
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the PCIe IP. Ports of core module are the top level ports for the PCIe IP.

DEVICE CORE: It coordinates and control interconnections between transmitter and receiver layers.

TL TX: It handles TLP packing,flow control,VC management and optional ECRC integrity.

TL RX: It processes received TLPs,Bad TLP packet discarding and receiver buffer handling.

DL TX: Generates DLLPs like FC and ack/nack.It will add sequence number and LCRC to TLP and also handles replay mechanism.

DL RX: It will process received TLPs and DLLPs.Schedules ACK/NACK for transmission.

TX PHY: It will pack data,order sets,tokens and K charecters.And handles scrambling,DC balance,tx lane reversal and tx pipeports. It also handles flit packing,flit CRC,ECC/FEC integrity,flit replay mechanism.

RX PHY: It will process received data and order sets,And handles descrambling,rx lane reversal,receive deskew and rx pipeports. It also handles flit unpacking,flit validation using flit sequence number,CRC,ECC/FEC integrity checks,flit ack/nack scheduling.

APP LAYER: It handles read and write requests between transaction layer and SoC interfaces.

SYNCHRONIZER: This module is used to synchronize the signals which are crossing clock domains.

CDM: It contains device capabilty and extended capability registers.

LBC: This module is used to access device capability and extended capability registers.

CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesCore Clock FrequencyPipe Clock FrequencySystem clock Frequency
TSMC 28nm162K1000MHz1000MHz500MHz
UMSC 55nm336K1000MHz1000MHz500MHz
SMIC 40nm187K1000MHz1000MHz500MHz

FPGA Device and FamilyLogic ResourcesCore Clock FrequencyPipe Clock FrequencySystem clock Frequency
AMD-xcvu9p-flga2104-2L-e26584 LUT's250MHz250MHz125MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.