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SDIO Device Controller IIP

Secure Digital Input Output Device Controller IIP

SDIO Device Controller IIP

Overview

It supports two types of data transmission mode:

1)SD mode

2)SPI mode

COMPETITIVE ADVANTAGE

The SivaKali Tech SDIO Device Controller IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Production Proven: Validated in silicon and FPGA across diverse applications.

Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.

Expert Support: Direct access to senior design engineers for rapid integration assistance.

Flexible Deliverables: Available as synthesizable source code or optimized netlists.

FEATURES
  • Compliant with Part 1 Physical Layer Specification Version 3.01 and earlier versions
  • Compliant with Part E1 SD Specification version 3.00 and earlier versions
  • Supports all commands/response types
  • Supports 1-bit, 4-bit SD bus mode and SPI Bus mode
  • Supports CRC7 checking/generation for command/response
  • Supports CRC16 checking/generation for data transfer
  • Supports default and high-speed modes
  • Supports SDR12, SDR25 ,DDR50, SDR 50 and SDR104 modes
  • Supports single byte, single block and multiple block transfer operations
  • Supports read-write and read-only cards
  • Supports different memory capacities given below,
    • Standard Capacity SD Memory Card (SDSC) : Up to 2 GB
    • High Capacity SD Memory Card (SDHC) : More than 2GB and up to 32GB
    • Extended Capacity SD Memory Card (SDXC) : More than 32GB and up to and including 2TB
  • Supports switch function command
  • Supports block count setting(CMD23) command
  • Supports direct commands during data transfer
  • Supports multiple IO functions and one memory
  • Supports Asynchronous Interrupt to Host Controller
  • Supports Suspend and Resume operation
  • Supports Read Wait control operation
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the SDIO Device Controller IIP. Ports of core module are the top level ports for the SDIO Device Controller IIP

CSR: CSR Module has all the registers and configurations. The timing of the transaction is stored in this module. Eg:- Command to Response – Ncr, Command to command – Ncc,Response to command – Nrc, Command to write and CRC status to next write data –Nwr, Command to read data and read data to next read data – Nac ..etc.

DMA CONTROLLER: The sampled write data of DSHIFTER will be written in the write FIFO which is done by DSHIFTER module. DMA controller reads the data written in the write FIFO and writes that data into the SoC Master, only if the CRC is matched. DMA controller reads the data from SoC Master and writes in the read FIFO. DSHIFTER reads the data from read FIFO and drives that data to the connected ports.

SUSPEND/RESUME: Suspend/Resume Function Module has the basic operation to suspend/resume data. If the command received with suspend operation enabled, This module enables the bit to suspend the data and the operation of resume also similar to the suspend by this module.

CFSM: CFSM module has the card Functional State Machine. Responses will be generated by this module. State of the card will be move based on the commands received. If the unsupported commands received or the commands are not met the expected conditions card status error bits will be updated based on the functionality

DATA FSM: DFSM Module enables the operation of write and reading of the data. Busy intimation for the write data will be send by this module to the DSHIFETR module. If CRC error occurs, write/read will not be get enabled. If abort received, it will move to the idle state.

CSHIFTER: CSHIFTER module samples the command from the host and driving the response which for the command received. It has the timers for driving response – Ncr. Calculation of response CRC has been done here. the received and calculated CRC is mismatch, card status will be update by this module. Once the end bit of command received , intimating to the CFSM for the state transition.

DSHIFTER: DSHIFTER Module samples write data and drives read data according to the commands.4/1 bit Data bus width is supported and supported SPI bus mode. Busy status is indicated by this module in DATA line[0]. When the abort received, the card will be stopped the read/write operation

LOCK: Lock/Unlock data will be processed by this module. Password match/mismatch,set/reset,erase,lock/unlocking the card were supported by this module.Lock/unlock failed error is supported by this module and updating in card status register.Old password from the CSR is checking with the new password received for the lock/unlock command . Setting the password for the locking card is done in this module If the password is mismatch lock/unlock bit will be set in the cardstatus register. If the abort command received not accepting the lock/unlock data.

PROGRAM CSD: Received CSD data will be send to the CSR using this module. If the abort command received, it will not accept the program csd data.The process of all the bits in CSD register is done by this module. Status of the CSD data will be updating to the CFSM module

Write PROTECT TIMER: Write Protect Group Module has the operation to check/update WP GRP enable and address. If SET_WRITE_PROT is in the process ,this module used to enable the corresponding WP GRP according to the command argument’s address.For the CLR_WRITE_PROT, this module checks the availability of the WP GRP and clears the Write protection for the particular address.This module keep all the WP GRP availability and giving it to the cfsm for SEND_WRITE_PROT operation.

Minimum COMMAND DELAY: Minimum command delay module calculates the command delays like N CC, N CR, N RC, and N ID. It gives the enable for the in between delay. When the delay gets completed it gets down and ready to do the transfers.

Voltage SWITCH TIMER: Voltage Switch timer implements the CMD11 operation. After CMD11 received, it will wait for the low period of configured value. Once the delay gets completed, it will intimate the Dshifhter, Cshifter and CFSM modules

IO FUNCTION: IO function module implements the FUNCTION_STATE machine to show the status of each functions. Once the IO function got enabled ,it waits for the function to get ready .If function got disabled in between the transaction, it moves to the disable state and also it indicates the status of read and write operations.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesSystem clock frequencyDMA clock frequencySDIO clock frequency
TSMC 28nm82.81K249.7Mhz249.7Mhz50Mhz
TSMC 180nm133.13K249.7Mhz249.7Mhz50Mhz
TSMC 130nm128K249.7Mhz249.7Mhz50Mhz
TSMC 90nm128K249.7Mhz249.7Mhz50Mhz
TSMC 12nm125.55K249.7Mhz249.7Mhz50Mhz
UMSC 55nm174.32K249.7Mhz249.7Mhz50Mhz
SMIC 40nm90.55K249.7Mhz249.7Mhz50Mhz

FPGA Device and FamilyLogic ResourcesClock Frequency
AMD-xcvu9p-flga2104-2L-e51685 LUT's187.25MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.