USB3.x HOST IIP

• USB 3.x Common support
• ->Compliant with USB 3.0/3.1/3.2 specification
• ->Supports Superspeed USB 3.0, SuperSpeedPlus 3.1, 3.2 and 3.0 OTG
• ->Configurable number of Configurations, Interfaces, Alternative Interfaces and Endpoints
• ->Configurable PIPE Interface width 8, 16 or 32 bits
• ->Supports Low frequency periodic signaling (LFPS) for initialization and power management(U1, U2 & U3)
• ->Supports Interrupt/Bulk/Isochronous/Control Transfers
• ->Control transfers supported by Endpoint 0
• ->Separate Endpoint Buffers for IN bound and OUT bound packets
• ->Supports lane polarity inversion
• ->Supports Bulk Streaming
• ->Supports extensible Host Controller Interface(xHCI)
• ->Supports Scrambler/Descrambler
• ->Option to enable/disable scrambling
• ->CRC checking and generation
• ->Supports Protocol Layer Error Handling.
• ->Provides prioritized scheduling for periodic endpoints.
• ->Separate round robin scheduling algorithm within Periodic and Non-periodic endpoints pipes.
• ->Supports PTM
• ->Implements Type 1 and 2 Buffers
• ->Supports LFPS Signaling, SCD/LBPM Messaging
• ->Supports Master and Slave Loopback mode for PHY layer testing
• ->Supports Compliance mode entry as per specification.
• ->Supports USB Suspend state and supports remote wakeup devices.
• ->Supports all SS/SSP Link Power Management States – U1, U2, U3
• ->Support for clock gating and multi-power-well support.
• ->Support DMA (Optional)
• ->Fully synthesizable.
• ->Static synchronous design.
• ->Positive edge clocking and no internal tri-states.
• ->Scan test ready.
• ->Simple host interfaces enable straightforward integration with microcontrollers and application processors.
• USB 3.0
• ->Supports Gen1 super speed with 5GT/s data rate
• ->Supports single lane
• ->Supports ADP,HNP,SRP and RSP
• ->Supports LCRD_A to LCRD_D Credits
• USB 3.1
• In addition to USB3.0 features,USB3.1 supports the following features
• ->Supports Gen2 with SuperSpeedPlus and Gen1 with Super speed
• ->Supports specific LFPS patterns(SCD1/SCD2) for Super speed plus ports
• ->Supports SuperSpeedPlus LFPS Based PWM Message (LBPM)
• ->Supports SuperSpeedPlus Precision Time Measurement
• ->Supports SuperSpeedPlus Transaction Reordering for periodic and asynchronous packet
• ->Supports Length field replica
• ->Supports Endpoint companion descriptor
• ->Supports Type-A and Type-B credits
• ->Supports 128B/132B Encoding/Decoding
• USB 3.2
• In addition to USB3.0 and USB3.1 features, USB 3.2 supports the following features.
• ->Supports Dual lane
• ->Supports Deskew buffer
• ->Supports Data striping in dual lanes
• ->Supports Configuration summary descriptor
• ->Supports link error count and soft error count
• ->Supports retimer connectivity models
• ->Supports all the Retimer state machine states[RTSM]
• ->Supports SRIS and Bit-Level Retimers functionality
• ->Supports Retimer presence announcement through LBPM Available as Additional Feature at extra cost
• ->Support additional functionality of Vendor Specific Request
• ->ISO26262 Functional safety(ASIL B/D)
• ->o ISO26262 Safety Manual (SAM) Document
• ->o ISO26262 Failure Modes, Effects and Diagnostics Analysis (FMEDA)
• ->Document
• ->FPGA Validation
• ->Memories with ECC
• ->Customer SoC I/F

CORE: Core module interconnects all the sub-modules in the USB3.x Host IP. Ports of core module are the top level ports for the USB3.x Host IP.

TRANSACTION SCHEDULER: Transaction scheduler is responsible for deciding which USB transaction is issued next by the host.

TRANSACTOR: Transactor module performs the transactions selected by the transaction scheduler.

EVENT CONTROL: Event controls are used to generate,queue and report the events from the host controller to software.

COMMAND PROCESSOR: Command processor executes the xHCI commands issued by the software through command ring.

SCRAMBLER/DE-SCRAMBLER: Scrambler Module is used to scramble/de-scramble the valid Order sets,control and data packets.

CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

RX DATA FRAMER: Rx data framer is used to decode all the valid data coming from PHY.

TX/RX SYNC FIFO: Tx and Rx sync fifo's are used to send data or receive data safely between different(CORE and PIPE) clocks.

LTSSM: LTSSM is the state machine controls the link behaviour between PHY and MAC.

OS GENERATOR/OS PROCESSOR: OS generator/processor is used to generate or process the Order set information.

LCW FRAMER: Lcw framer is used to frame the packets according to the specifications.

LC DECODER: Lc decoder is responsible for checking the received Link Command Words.

TX DATA FRAMER: Txdata framer is used to constructs the proper format of header packet.

CRC5/CRC16 GENERATOR/CHECKER: Crc5/16 generator/checker used to generate/check the CRC5(Cyclic Redundancy Check) and CRC16(Cyclic Redundancy Check) of the Link control word and Header packets.

LMP GENERATOR: Lmp generator is used to generate the Link Management Packet for link management and link control.

DATA PACKET DECODER: Data packet decode is used to identify and detects the errors in packet type.CRC check,sequence numbers.

CRC32 GENERATOR/CHECKER: Crc32 generator/checker used to generate/check the CRC32(Cyclic Redundancy Check) for the payload of Data packets.

• Single Site license for regional development teams.
• Multi-Site license for global corporate deployments.
• Single Design license for specific project cost-efficiency.
• Unlimited Design license for high-volume product roadmaps.

• Complete Verilog/VHDL/SystemC Source Code.
• UVM-compliant verification environment with a comprehensive test suite.
• Production-ready synthesis, Lint, and CDC scripts.
• IP-XACT RDL generated address maps.
• Standard-compliant firmware and Linux/C driver packages.
• Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.