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eSPI Controller IIP

Enhanced Serial Peripheral Interface Controller IIP

eSPI Controller IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech eSPI Controller IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. The backbone of system control and peripheral connectivity for any SoC. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Ultra-Low Gate Count: Extremely efficient implementation, negligible impact on total SoC area.

Simple Integration: Standard AMBA (APB/AHB) or AXI-Lite interfaces for plug-and-play system connectivity.

Proven Reliability: Thousands of production deployments ensuring rock-solid stability.

Driver Support: Includes bare-metal and Linux drivers to accelerate software development.

FEATURES
  • Compliant with eSPI base specification as defined in Enhanced Serial Peripheral Interface (eSPI) Specification rev.1.5
  • Supports Master and Slave Modes
  • Supports Single, Dual and Quad Modes
  • Supports different types of resets as per spec,
    • eSPI reset from Master to Slave
    • eSPI reset from Slave to Master
    • In-band reset command
  • Supports baud rate selection
  • Supports TX and RX operation as per specs
  • Supports below transaction phases,
    • Command Phase
    • Turn-Around Phase
    • Response Phase
  • Supports Slave triggered transaction
  • Supports Interrupts and Alert
  • Supports below multiple channels,
    • Peripheral channel
    • Virtual Wires channel
    • Out Of Band message channel
    • Flash Access channel
  • Supports CRC checking
  • various kinds of Master and Slave errors detection and handling
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors
FUNCTIONAL DESCRIPTION

CORE: Core Module interconnects all the sub-modules in the eSPI Slave IP. Ports of core module are the top level ports for the eSPI Slave IP.

FSM: FSM Module sample and drive the eSPI transcations to eSPI Master. This blocks implements all the features of eSPI specifications. This block has MFSM and SFSM module

PRESCALER: Prescaler module is used to divide the system clock based on the given prescaler value to derive the serial clock input for eSPI.

CSR: CSR Module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesSystem Clock FrequencySCK Clock Frequency
TSMC 28nm11.43K264MHz66MHz
UMSC 55nm20.09K264MHz66MHz
SMIC 40nm12.18K264MHz66MHz

FPGA Device and FamilyLogic ResourcesClock Frequency
AMD-xcvu9p-flga2104-2L-e51685 LUT's100MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.