MIPI ASPMI Slave IIP

• MIPI ASPMI Slave IIP v2.3 r0.0.8
• Compliant with 2.3 revision 0.0.8 ASPMI Slave Specification
• Full MIPI SPMI 2.0 Slave functionality
• Supports following frames
• Command Frame
• Data/Address Frame
• No Response Frame
• Supports ACK/NACK as per 2.0 specs
• Support for slave requests through Alert(A) / Slave Request(SR) bit
• Support for Slave Request Hold.
• Glitch suppression (optional).
• Supports extended register read/writes
• Supports wakeup command
• Supports Authentication Command Sequence
• Supports Device Descriptor Block command Sequences
• Supports following Device Interrupts
• Edge sensitive interrupts
• Level sensitive interrupts
• Group interrupts
• SPS (System Power State) interrupts
• DVC Group interrupts
• LDO and DVC interrupts
• Interrupt priority queuing
• IRQH Enable register (Disabling of IRQ generation functionality based on NACK Retry limit)
• Generation of Group event on any internal SPMI error logged in an ERROR CTRL register
• Supports virtual wires on SPMI (Supports both scheme 1 and scheme 2)
• Supports Short Addressing Modes
• Supports Control on Register0 write and power mode command (Sleep/Wakeup/Shutdown/Reset) reception
• Supports Slave To Slave (STS) Transmit and Receive Command filtering
• Supports SGPIO functionality
• Ability to generate an empty arbitration request
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Simple host interfaces enable straightforward integration with microcontrollers and application processors
• Optionally this core can be built to have SPI or I2C interface for application where slave can have multiple interfaces like SPMI or SPI or I2C Interface.
• This core achieves ASIL B and can be made to achieve ASIL D as per ISO26262

CORE:

Core module interconnects all the sub modules (START, FSM, REQ, SDA OUT and CSR) inside the Slave IP. Ports of core module are the top level ports of Slave IP. Core module includes following functionalities,

• Logic for SDA output enable (o_sda_en)
• Reset generation

CSR: CSR module has all the configuration registers of Slave IP, Interrupt status registers and RCS State Machine. Also it has the logic to run TBT timer, and Apple Supported features

• Optionally NOCSR version can be provided - Where there will be no internal/physical registers inside the Slave core, all the control and data information are enabled using top level interfaces

FSM: FSM module process SPMI commands once SSC is detected. FSM responds to SPMI commands (ACK/NACK for Write transfer and Read data for read transfer) only if Slave ID is matched with the ID driven on the SPMI bus by the Master/RCS, else FSM silently trace SPMI transaction.

REQ: Request FSM process the RCS pending transaction. It comprises two procedural blocks. One block monitors the Arbitration phase and the other processes the Pending transfer if RCS wins the arbitration.

START: Start module detects the SSC and arbitration start condition on SPMI bus. Start detect and arbitration start signals from this module triggers Slave FSM, REQ FSM and RCS FSM (arbitration handling) to process a SPMI transaction.

SDA_OUT: SDA OUT module is to enable / disable SDA driver based on the signals from FSM, Request FSM and CSR Module. It is the block where value onto Slave’s SDA bus is loaded as per the value provided through the ports from FSM, Request FSM and CSR Module.

• Single Site license for regional development teams.
• Multi-Site license for global corporate deployments.
• Single Design license for specific project cost-efficiency.
• Unlimited Design license for high-volume product roadmaps.

• Complete Verilog/VHDL/SystemC Source Code.
• UVM-compliant verification environment with a comprehensive test suite.
• Production-ready synthesis, Lint, and CDC scripts.
• IP-XACT RDL generated address maps.
• Standard-compliant firmware and Linux/C driver packages.
• Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.