FEC RS (544,514) IIP

IEEE 802.3 Ethernet KP FEC

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech FEC RS (544,514) IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Production Proven: Validated in silicon and FPGA across diverse applications.

Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.

Expert Support: Direct access to senior design engineers for rapid integration assistance.

Flexible Deliverables: Available as synthesizable source code or optimized netlists.

FEATURES

Compliant with CPRI Specification V7.0, IEEE Standard 802.3.2018 Ethernet specification and JESD204D Specification
Supports full FEC functionality.
Supports Reed Solomon (544,514) FEC, 10-bit symbols.
Supports different input and output data widths of multiples of 10-bits.
Supports the parity generation of 300 bits.
Supports the bit locker mechanism.
Supports the Syndrome calculation.
Supports the Berlekamp's algorithm.
Supports the Chien search for error position.
Supports the Error correction of 150 bits.
Supports up to the 15 symbols of error correction.
Supports the pipelined mechanism for the error correction.

FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the FEC_RS (544,514) IP. Ports of core module are the top level ports for the FEC_RS (544,514) IP.

ENCODER: Encoder module is used to encode the input data and calculate the parity.

GALIOS MULTIPLIERS: It is used in encoder to calculate parity symbols using galios multiplication and input data and in decoder to compute syndromes and error values.

STATE REGISTERS: State registers are used in encoder to store intermediate parity states while processing the data symbols sequentially.

CONTROLLER: It resets the encoder state registers at right time so each codeword is encoded correctly without mixing data from different frames.

DECODER: Decoder module is used to detect and correct the errors with the help of syndrome calculation.

BIT LOCKER: Bit Locker is used to lock the correct codeword.

SYNDROME CALCULATOR: Syndrome Calculator is used to detect the error.

KEY SOLVER: Key solver is used to solve key equation, which determines the error-locator and error-evaluator polynomials.

ERROR CORRECTION: Error correction is used to correct the error.

ASIC AND FPGA IMPLEMENTATION

ASIC Technology	Logic Resources	System Clock Frequency	Encoder Clock Frequency	Decoder Clock Frequency
TSMC 28nm	74.05K	1GHz	1GHz	1GHz
UMC 55nm	178.24K	1GHz	1GHz	1GHz
SMIC 40nm	105.05K	1GHz	1GHz	1GHz

Logic Resources	System Clock Frequency	Encoder Clock Frequency	Decoder Clock Frequency
12341.667 LUT's	1GHz	1GHz	1GHz

LICENSING OPTIONS

Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.

DELIVERABLES

Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.