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MIPI APHY GPIO PAL IIP

MIPI APHY GPIO PAL IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech MIPI APHY GPIO PAL IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Ideal for mobile, automotive, and IoT applications requiring high-bandwidth camera and display interfaces. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Low Power & High Efficiency: Optimized for mobile and battery-operated devices with advanced power gating and low-leakage architecture.

Silicon Proven: Validated on leading foundry nodes (5nm, 7nm, 12nm, 28nm), ensuring reduced integration risk.

Comprehensive Support: Full compliance with latest MIPI Alliance specifications, including CSI-2, DSI-2, and I3C.

Flexible Licensing: Cost-effective, royalty-free licensing models compared to restrictive tier-1 vendor options.

FEATURES
  • The GPIO interfaces with the A-PHY Data Link Layer via the APPI Interface (As per the A-PHY Specification [MIPI05])
  • Supports the below feature modes
  • Over sampled mode
  • Even pattern mode
  • Supports the below paths
  • TO_APHY_PATH(TAP)
  • FROM_APHY_TAP(FAP)
  • Supports the GPIO Adaptation Layer Register list
  • Supports Oversampling Rate
  • Supports Error Handling
  • Supports GPIO Keep Alive Timing
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the MIPI APHY GPIO PAL IIP. Ports of core module are the top level ports for the MIPI APHY GPIO PAL IIP.

PACK: Packing function process the raw data and formatting into a standardized A-packets.

UNPACK: It extracts the raw SEP application data from the incoming A-packet stream and sends through the GPIO low level packet interface.

CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesSystem clock frequencyAppi clock frequency
TSMC 28nm43K125MHz31.25MHz
UMSC 55nm123K125MHz31.25MHz
SMIC 40nm68K125MHz31.25MHz

FPGA Device and FamilyLogic ResourcesSystem clock frequencyAppi clock frequency
AMD-xcvu9p-flga2104-2L-e7166 LUT's125MHz31.25MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.