The SivaKali Tech PSRAM Controller IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Optimized for high-performance computing, storage appliances, and mobile SoCs. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.
COMPETITIVE ADVANTAGE
Maximum Bandwidth: Intelligent controller architecture maximizes bus utilization and minimizes latency.
Data Integrity: Advanced ECC (Error Correction Code) and reliability features for enterprise-grade data protection.
Broad Compatibility: Supports a wide range of JEDEC standard memory devices from major vendors.
PHY Independent: DFI-compliant interface allows easy integration with third-party or foundry-provided PHYs.
FEATURES
Compliant with PSRAM protocol standard Specifications
Supports below Interfaces:
SPI/QPI with SDR mode
Octal SPI with DDR Octal RAM mode, two bytes transfers per one clock cycle
Supports clock rate up to 200MHz, 400MB/s read/write throughput
Supports below organizations:
16Mb, 2M x 8bits
64Mb, 8M x 8bits
64Mb, 8M x 8bits with 1024 byte page size - Column address: AY0 to AY9 - Row address : AX0 to AX12
Supports self-refresh Mode
Supports software reset
Supports Data Mask (DM) for write data
Supports Data strobe (DQS) enabled high-speed read operation
Reset pin available Register Configurable write and read initial latencies
Supports below Write Burst Length
Maximum 1024 Bytes
Minimum 2 Bytes
Supports Wrap & Hybrid Burst in 16/32/64/128 lengths Supports Linear Burst Command (wraps at page boundary)
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors
FUNCTIONAL DESCRIPTION
CORE: Core module interconnects all the sub-modules in the PSRAM IP. Ports of core module are the top level ports for the PSRAM IP.
FSM: PSRAM IP generates specific command sequences and manages variable operations. Drives PSRAM IP command/address signals and handles bidirectional data transfer over the PSRAM data bus.
CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.
ASIC AND FPGA IMPLEMENTATION
ASIC Technology
Logic Resources
System Clock Frequency
TSMC 28nm
22.52K
133MHz
UMSC 55nm
41.08K
133MHz
FPGA Device and Family
Logic Resources
Clock Frequency
AMD-xcvu9p-flga2104-2L-e
51685 LUT's
187.25MHz
LICENSING OPTIONS
Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.
