PCS UCIe IIP

• Supports specification version 1.0, 1.1, 2.0 and 3.0
• Supported Package - Standard package, Advanced Package
• Supported Flit Format
• Raw Format
• 68B Flit Format
• Standard 256B End Header Flit Format
• Standard 256B Start Header Flit Format
• Latency-Optimized 256B without Optional Bytes Flit Format
• Latency-Optimized 256B with Optional Bytes Flit Format
• Supports 4 GT/s, 8 GT/s, 12 GT/s, 16 GT/s, 24 GT/s, 32 GT/s, 48 GT/s and 64GT/s speeds with
• 500 MHz, 1 GHz, 1.5 GHz, 2 GHz, 3 GHz, 4 GHz, 6GHz and 8 GHz UCIe clock frequency
• Supports 16 Lanes, 32 Lanes and 64 Lanes
• Supports link initialization, training and power management states
• Supports Sideband messaging for link training
• Support byte to lane mapping for data transmission over lanes
• Supports data scrambling on the transmit path and descrambling on the receive path
• Support lane reversal
• Supports sync fsm in receiver path to lock correct bit position
• Supports link width degradation
• Supports all Vendor defined Sideband messages
• Support Positive edge clocking and no internal tri-states
• Scan test ready
• Fully synthesizable
• Static synchronous design
• Simple interface allows easy connection to microprocessor/ microcontroller devices

CORE: Core module interconnects all the sub-modules in the PCS UCIe IP. Ports of core module are the top level ports for the PCS UCIe IP.

PCS Register: This module has all the Control and status registers. It maintains all the configuration and monitoring registers used by the UCIe IP.This block contains interrupt enable and status registers.

Link Training State Machine: The Link Training State Machine module controls PCS link initialization, calibration, and maintenance. It manages lane discovery, alignment, scrambling synchronization, and transitions to the active state, as well as retraining and error recovery.

Byte-to-Lane Mapping: The Byte-to-Lane Mapping module distributes outgoing byte data from the D2D Adapter across the active physical lanes using deterministic striping, enabling parallel data transmission with guaranteed ordering.

Scrambler: The Scrambler module randomizes outgoing data using polynomial to improve signal integrity.

Lane Reversal: The Lane Reversal module applies the logical-to-physical lane mapping determined during link training, ensuring correct data placement on the physical lanes prior to transmission.And also it reorders incoming lane data to restore correct logical lane ordering within the PCS.

Sync FSM: The Sync FSM module establishes and maintains receiver side synchronization by detecting alignment patterns across all active lanes. It performs byte and lane alignment and ensures stable synchronization before releasing data to the D2D Adapter.

Descrambler: The Descrambler module restores the original data stream while maintaining synchronization with the remote transmitter.

Lane-to-Byte Mapping: The Lane-to-Byte Mapping module reassembles striped multi-lane receive data into a contiguous byte stream. It preserves deterministic byte ordering and supports negotiated lane configurations.

• Single Site license for regional development teams.
• Multi-Site license for global corporate deployments.
• Single Design license for specific project cost-efficiency.
• Unlimited Design license for high-volume product roadmaps.

• Complete Verilog/VHDL/SystemC Source Code.
• UVM-compliant verification environment with a comprehensive test suite.
• Production-ready synthesis, Lint, and CDC scripts.
• IP-XACT RDL generated address maps.
• Standard-compliant firmware and Linux/C driver packages.
• Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.