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UFS Device IIP

UFS Device IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech UFS Device IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Production Proven: Validated in silicon and FPGA across diverse applications.

Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.

Expert Support: Direct access to senior design engineers for rapid integration assistance.

Flexible Deliverables: Available as synthesizable source code or optimized netlists.

FEATURES
  • UFS Device v4.0 Supports full UFS Device functionality
  • Supports UFS driver layer over UniPro
  • AXI 4.0 Interconnect for data transfer
  • APB/AXI Lite Interface for register access
  • Supports configurable Cport
  • Supports complete control of UIC Layer by UFS Device
  • Supports VIP interface at MPHY Serial, MPHY RMMI, Unipro CPort level
  • Supports UFS-Specified commands of Specification JESD220C [Version 2.1]
  • Supports UFS-Specified commands of Specification JESD220D [Version 3.0]
  • Supports UFS-Specified commands of Specification JESD220E [Version 3.1]
  • Supports UFS-Specified commands of Specification JESD220F [Version 4.0]
  • Supports Unified Memory Extension JESD220-1A (Version 1.1)
  • All UPIU Processing:
    • Datain, Dataout, Command, Response, RTT, Query, Task Management and Reject
  • Supports various UFS layers:
    • UFS Command Set Layer (UCS)
    • UFS Transport Protocol Layer (UTP)
    • UFS Interconnect Layer (UIC)
  • Supports boot mode operation
  • Supports device enumeration and discovery
  • Priority arbitration between command, query and task management UPIUs and indexed based processing within Command and Query UPIUs
  • Supports 32 UTP Transfer request descriptors and 8 UTP Task Management Descriptors for UFS host
  • Supports up to 256 outstanding commands [not configurable]
  • Supports 8/32 LUN
  • Maximum number of RTT supported is 32
  • Supports Multiple partitions (LUNs) with partition Management
  • Supports Multiple User Data Partition with Enhanced User Data Area options
  • Supports boot partitions
  • Supports Reliable write operation
  • Supports Background operations
  • Supports Secure operations, Purge and Erase to enhance data security
  • Supports Write Protection options, including Permanent & Power-On Write Protection
  • Supports Signed access to a Replay Protected Memory Block
  • Supports HW Reset Signals
  • Supports Task management operations
  • Supports Power management operations
  • Supports automatic/user tag generation
  • Supports all Initiator ID values
  • Supports UFSHCI as per the specification JESD223E
  • Supports Priority LUN handling
  • Supports below latest 4.0 Version features:
    • HighSpeed-LinkStartup control
    • EXT_IID with Initiator ID
    • Hint
  • Supports below UFS Version 3.1 features:
    • UFS-Deep Sleep Power Mode
    • Performance Throttling Event Notification
    • Write Booster
    • Refresh Operation
  • Supports HPB version 1.0 and 2.0 as per latest spec
  • Error injection and detection in all levels of UFS protocol
  • Notifies the testbench of significant events such as transactions, warnings,timing and protocol violations
  • Supports constraints Randomization
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the UFS Device IIP. Ports of core module are the top level ports for UFS Device IIP

CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality

CMD AXI HANDLER: Cmd Axi Handler module will initiate the request for AXI interface and handle the data from AXI Interface

DECODER: Decoder module will decode the incoming UPIU's

ENCODER: Encoder module will encode the fields for every UPIU's

DMA QUEUE HANDLER: DMA Queue Handler module will handle the command transfers for the current transaction

UIC PROCESSOR: Uic processor module will be responsible for initiating UIC commands related to UniPro and track the status of UniPro

AXI Master: AXI Master module will initiated request to AXI Slave for both read and write transactions and performs the beat calculation, boundary cross check based on the requested ID for read request and write request

AXI Lite Slave: AXI Lite Slave module will handles UFS Registers write and read operations from AXI Lite Master

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesSystem Clock FrequencyReference Clock Frequency
TSMC 28nm254.69K400MHz62.5MHz
UMSC 55nm507.57K400MHz62.5MHz
SMIC 40nm211.02K400MHz62.5MHz

FPGA Device and FamilyLogic ResourcesSystem Clock FrequencyReference Clock Frequency
AMD-xcvu9p-flga2104-2L-e42448 LUT's150MHz62.5MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.