The SivaKali Tech AVSBUS Slave IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.
COMPETITIVE ADVANTAGE
Production Proven: Validated in silicon and FPGA across diverse applications.
Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.
Expert Support: Direct access to senior design engineers for rapid integration assistance.
Flexible Deliverables: Available as synthesizable source code or optimized netlists.
FEATURES
Compliant with AVSBus specification as defined in version 1.3.1 Part III of PMBus Bus Specification
Full AVSBus Slave Functionality
Supports 3-wire ,2-wire AVSBus interface Supports Multiple back to back frames and status for higher bus efficiency up to 256 Commands and responses
Supports all AVSBus Commands as per specification
Supports all AVSBus Data types as per specification
Support Slave status response frames
Supports Slave pin zero interrupt
Supports Clock Resynchronization
Support Bus timeout function
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors
FUNCTIONAL DESCRIPTION
CORE: Core module interconnects all the sub-modules in the Slave IP. Ports of core module are the top level ports for the Slave IP.
CSR: CSR module has all the configuration registers of Slave and Interrupt status registers and AVSBus commands registers used for write and read operation.
FSM: FSM module process AVSBus Slave commands once start is detected. FSM responds to AVSBus Slave commands (ACK/NACK for Write transfer and transmits read data for read transfer).
ASIC AND FPGA IMPLEMENTATION
ASIC Technology
Logic Resources
Clock Frequency
AVS Clock Frequency
TSMC 12nm
10.61K
100MHz
50MHz
TSMC 28nm
6.97K
100MHz
50MHz
TSMC 90nm
9.96K
100MHz
50MHz
TSMC 130nm
9.96K
100MHz
50MHz
TSMC 180nm
10.40K
100MHz
50MHz
GF 180nm
7.81K
100MHz
50MHz
SMIC 40nm
7.51K
100MHz
50MHz
UMSC 55nm
12.90K
100MHz
50MHz
FPGA Device and Family
Logic Resources
Clock Frequency
AMD-xcvu9p-flga2104-2L-e
1161 LUT's
100MHz
LICENSING OPTIONS
Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.
