MIPI APHY I2C MASTER PAL IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech MIPI APHY I2C MASTER PAL IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Ideal for mobile, automotive, and IoT applications requiring high-bandwidth camera and display interfaces. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Low Power & High Efficiency: Optimized for mobile and battery-operated devices with advanced power gating and low-leakage architecture.

Silicon Proven: Validated on leading foundry nodes (5nm, 7nm, 12nm, 28nm), ensuring reduced integration risk.

Comprehensive Support: Full compliance with latest MIPI Alliance specifications, including CSI-2, DSI-2, and I3C.

Flexible Licensing: Cost-effective, royalty-free licensing models compared to restrictive tier-1 vendor options.

FEATURES

The I2C interfaces with the A-PHY Data Link Layer via the APPI Interface (As per the A-PHY Specification [MIPI05])
Supports I2C master bi-directional data transfers
Supports ICA A-Packets

Single byte payload format
Multi-Byte payload format

Supports the following features

ICAM (I2C Adaptation Layer that is natively connected to an I2C master device)

Supports the below transaction types

Reserved
Standard Mode
Full-speed/Fast mode
Fast mode/Fast mode plus
High-speed Mode
Ultra-fast mode

Supports the following Mechanisms

Stretching
Stalling

Supports Master-to-slave and Slave-to-master byte termination mode
Supports ICA register list
Supports the following multi-session mode

ICAM multi-session modes

Supports error handling
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors

FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the MIPI APHY I2C MASTER PAL IIP. Ports of core module are the top level ports for the MIPI APHY I2C MASTER PAL IIP.

TU(Tunneling/Unifying): Tunneling and unifying acts as bridge within the I2C Adaptation layer for conversion between SEP (Service extension packets) and Non-SE. It will operates in any of three modes(Transparent,Legacy,Mixed modes) based on the Reception of SEP or Non -SEP packets.

CHUNK: Chunking function divides the raw data it into multiple chunks, each individual chunk is placed into its own A- packet and assigned an order value field in A- packet header

PACK: Packing function process the RAW data and formatting it into a standardized A-packets.

UNPACK: It extracts the raw SEP application data from the incoming A-packet stream.

CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

ASIC AND FPGA IMPLEMENTATION

ASIC Technology	Logic Resources	System clock frequency	Appi clock frequency
TSMC 28nm	45K	125MHz	31.25MHz
UMSC 55nm	136K	125MHz	31.25MHz
SMIC 40nm	87K	125MHz	31.25MHz

FPGA Device and Family	Logic Resources	System clock frequency	Appi clock frequency
AMD-xcvu9p-flga2104-2L-e	7500 LUT's	125MHz	31.25MHz

LICENSING OPTIONS

Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.

DELIVERABLES

Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.