The SivaKali Tech SGPIO Initiator IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. The backbone of system control and peripheral connectivity for any SoC. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.
COMPETITIVE ADVANTAGE
Ultra-Low Gate Count: Extremely efficient implementation, negligible impact on total SoC area.
Simple Integration: Standard AMBA (APB/AHB) or AXI-Lite interfaces for plug-and-play system connectivity.
Proven Reliability: Thousands of production deployments ensuring rock-solid stability.
Driver Support: Includes bare-metal and Linux drivers to accelerate software development.
FEATURES
Compliant with SFF-8485 Specification for Serial GPIO (SGPIO) Bus revision 0.7
Supports up to 256 hard disks
Supports various operating frequency from 32Hz to 100KHz
Supports to control High time and Low time of SGPIO Clock
Supports transmit on rising edge and sample on falling edge
Supports SGPIO LOAD to 0, when not exchanging a bit stream
Supports SGPIO LOAD to 1, when SGPIO bus is not used
Supports two blink generators A and B, used to control the output patterns
Support two different modes
Normal Mode
General Purpose Mode
Supports below different types of registers,
Configuration registers
Receive registers
General purpose receive registers
Transmit registers
General purpose transmit registers
various kinds of errors detection and interrupt handling
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors
This core achieves ASIL B and can be made to achieve ASIL D as per ISO26262
FUNCTIONAL DESCRIPTION
CSR: CSR module has the set of registers used to configure GPIO core, log the GPIO status, program the timeout value for Host and register to store the GPIO data.
CORE: Core module interconnects all the sub-modules in the Peripheral IP. Ports of core module are the top level ports for the Peripheral IP and the Core Module acts as the central interconnect hub.
FSM: FSM module generates the SGPIO transactions on based on pending transfers from CSR block. This blocks implements the features of SGPIO spec.
PRESCALER: Prescaler module is used to divide the system clock based on the given prescaler value to derive the serial clock input.
ASIC AND FPGA IMPLEMENTATION
ASIC Technology
Logic Resources
Clock Frequency
TSMC 28nm
2.34K
48MHz
UMSC 55nm
2.34K
48MHz
SMIC 40nm
2.34K
48MHz
FPGA Device and Family
Logic Resources
Clock Frequency
AMD-xcvu9p-flga2104-2L-e
12654 LUT's
48MHz
LICENSING OPTIONS
Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.
