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VESA DSC Decoder IIP

VESA Display Stream Compression Decoder IIP

VESA DSC Decoder IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech VESA DSC Decoder IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Production Proven: Validated in silicon and FPGA across diverse applications.

Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.

Expert Support: Direct access to senior design engineers for rapid integration assistance.

Flexible Deliverables: Available as synthesizable source code or optimized netlists.

FEATURES
  • VESA DSC Version 1.2a Decoder
  • Fully compliant with the VESA Display Stream Compression Decoder Versions 1.1, 1.2, 1.2a and 1.2b specification and ensures standard-adherent operation across all supported configurations.
  • Backward compatible with DSC v1.1.
  • Dynamically supports slice configurations of 1, 2, 4, 8, 12, 16, 20, 24.
  • Supports configurable output pixel processing of 3 pixels per clock.
  • Supports maximum display resolution up to 8K.
  • Compatible with the video formats which are mentioned in 1.2b version,
  • ->RGB (8, 10, 12, 14 and 16 bits per component)
  • ->YCbCr 4:2:2 simple (8, 10, 12, 14 and 16 bits per component)
  • ->YCbCr 4:2:2 native (8, 10, 12, 14 and 16 bits per component)
  • ->YCbCr 4:2:0 native (8, 10, 12, 14 and 16 bits per component)
  • Supports below coding schemes,
    • Modified Median-Adaptive Prediction (MMAP)
    • Block Prediction (BP)
    • Midpoint Prediction (MPP)
    • Indexed Color History (ICH)
  • Supports programmable compressed bit rate of 8bpp and higher (6bpp and higher for 4:2:0 pictures).
  • Supports Input Buffering compatible with transport stream over video interfaces like HDMI2.1, MIPI DSI and DisplayPort.
  • Verified with VESA DSC 1.2a C model using sample images.
  • Supports PPS 128 bytes block decoding.
  • Fully synthesizable.
  • Static synchronous design.
  • Positive edge clocking and no internal tri-states.
  • Scan test ready.
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors.
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the DSC DECODER IP. Ports of core module are the top level ports for the DSC DECODER IP.

CSR: CSR contains all Control and Status Registers (CSRs). It decodes CPU-driven configuration commands and maps them to functional output signals across the IP.

RATE_BUFFER: Rate buffer module temporarily stores the incoming DSC bitstream and regulates the data flow to match the decoder processing rate, preventing underflow and overflow.

SUBSTREAM_DEMULTIPLEX: Substream demultiplex module separates the multiplexed bitstream into component substreams(Y, Co, Cg or RGB) and groups for parallel decoding.

VLD_ENTROPY_DECODER: VLD module decodes DSU-VLD encoded symbols from the bitstream to recover quantized residual and control information.

RATE_CONTROL: Rate control module manages decoder buffer behavior and aligns decoding with the encoder's rate model to ensure compliant and stable reconstruction.

PREDICTION: Prediction module reconstructs pixel values by applying DSC prediction methods(MMAP, Block Prediction, Midpoint Prediction and Index Color History) combined with decoded residuals.

LINE_BUFFER: Line buffer module stores previously reconstructed pixels from the current and previous lines to support Prediction, Flatness Detection, Rate Control, Index Color History(ICH) and slice-based processing.

CSC: CSC module converts decoded pixels from YCoCg-R to RGB format.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesSystem Clock FrequencyPixel Clock FrequencyBitstream Clock Frenquency
TSMC 28nm258.38K100MHz200MHz33.33MHz
UMSC 55nm588.45K100MHz200MHz33.33MHz
SMIC 40nm278.56K100MHz200MHz33.33MHz

FPGA Device and FamilyLogic ResourcesSystem Clock FrequencyPixel Clock FrequencyBitstream Clock Frequency
AMD-xcvu9p-flga2104-2L-e43063 LUT's100MHz200MHz33.33MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.