H264 ENCODER IIP

• Advanced video coding for generic audiovisual services
• Fully compatible with the ITU-T H.264 (V15)(08/2024) specification and ensures standard-adherent operation across all supported configurations.
• Supports all Profiles and levels upto 6.2.
• Dynamically supports multiple slice configurations
• Supports configurable input pixel processing of 4,8 and 16 pixels per clock
• Supports configurable output bitstream processing of 32,64 and 128 bits per clock
• Supports Variable Bit Rate and Constant Bit Rate.
• Supports maximum resolution upto 8k@120Hz.
• Compatible with the video formats which are mentioned in V15.
• YCbCr 4:4:4 (24,30,36,42 Bits Per Pixel).
• YCbCr 4:2:2 (16,20 Bits Per Pixel).
• YCbCr 4:2:0 (12 Bits Per Pixel).
• Y(Monochrome) (8,10,12 Bits Per Pixel).
• Supports both intra and inter prediction process.
• Supports SATD/SAD for Rate Distortion Optimization(RDO).
• Supports CAVLC/CABAC entropy process.
• Supports block skipping logic for lower bitrate.
• Supports De-blocking filter for better quality.
• Supports picture cropping for image sizes that are not a multiple of 16 pixels.
• Supports Chroma Quantization Parameter offset for increased compression.
• Fully synthesizable.
• Static synchronous design.
• Positive edge clocking and no internal tri-states.
• Scan test ready.
• Simple interface allows easy connection to microprocessor/microcontroller device.

CORE: Core module interconnects all the sub-modules in the H264 Encoder IIP. Ports of core module are the top level ports for the H264 Encoder IIP.

MACROBLOCK CONVERSION : Macroblock Conversion module used for conversion reorders standard row by row pixels into 16x16 blocks to prepare video data.

PREDICTION : Prediction module performs intra prediction for luma and chroma blocks. It computes prediction samples for all supported prediction modes.

TRANSFORMATION : The Transformation module converts spatial pixels into frequency coefficients, allowing for efficient data compression by discarding visually insignificant high frequency information.

QUANTIZATION: Quantization module is used to perform the quantization process based on the quantization parameter(QP).

DE-QUANTIZATION: Dequantization module is used to restores the scale of quantized coefficients by applying inverse quantization method using the dequantization parameter.

INVERSE TRANSFORMATION: Inverse Transformation module converts dequantized transform coefficients back to reconstruct the prediction residual.

DE-BLOCKING FILTER: De-Blocking module removed the visible, blocky edges between compressed sections to make the video look smooth and natural.

RECONSTRUCTION: Reconstruction module rebuilds the frame by adding the residual data from inverse transformation and predicted data from prediction block.

CAVLC: CAVLC module used to perform the entropy coding and it encodes, compresses the quantized coefficients and send it to the bit stream.

BYTE STREAM NAL: Byte Stream NAL module used to encodes specific start codes to video packets so the decoder can easily find where data ends and begins in continuous stream

CSR: The CSR module contains all control and status registers. These registers used to control the RTL functionality and to monitor its status.

• Single Site license for regional development teams.
• Multi-Site license for global corporate deployments.
• Single Design license for specific project cost-efficiency.
• Unlimited Design license for high-volume product roadmaps.

• Complete Verilog/VHDL/SystemC Source Code.
• UVM-compliant verification environment with a comprehensive test suite.
• Production-ready synthesis, Lint, and CDC scripts.
• IP-XACT RDL generated address maps.
• Standard-compliant firmware and Linux/C driver packages.
• Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.