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V-By-One Transmitter IIP

V-By-One high-speed (HS) Transmitter IIP

V-By-One Transmitter IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech V-By-One Transmitter IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Delivering premium visual experiences for digital signage, broadcast, and consumer displays. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

High Quality Compression: Visually lossless compression algorithms optimized for minimal silicon area.

Real-Time Performance: Ultra-low latency processing suitable for live streaming and interactive applications.

Multi-Standard Support: Configurable to support various resolutions, frame rates, and color formats.

Power Efficient: Architecture optimized to minimize power consumption for portable multimedia devices.

FEATURES
  • V-By-One HS Version 1.4 Transmitter
  • Fully compliant with the HS Version 1.2, 1.3 and 1.4 specification and ensures standard-adherent operation across all supported configurations.
  • Dynamically supports lane configurations of 1, 2, 4, 8, 16 and 32 lanes.
  • Supports link rates from 600Mbps to 4Gbps.
  • Dynamically supports multiple byte modes 3, 4 and 5.
  • Supports configurable input pixel processing of 1, 2, 4 and 8 Pixels Per Clock (PPC).
  • Supports programmable parallel interface widths of 20bits, 40bits and 80bits.
  • Supports maximum resolution up to 4k@240Hz.
  • Compatible with the video formats which are mentioned in V-By-One HS Version 1.4.
    • RGB 4:4:4 (18,24,30,36 Bits Per Pixel)
    • YCbCr 4:4:4 (18,24,30,36 Bits Per Pixel)
    • YCbCr 4:2:2 (16,20,24,32 Bits Per Pixel)
    • RGBW/Y 4:4:4:4 (32,40 Bits Per Pixel)
  • Performs the scrambler and 8b/10b encoder.
  • Supports color and control data mapping allocation to the 3D flag.
  • Fully synthesizable.
  • Static synchronous design.
  • Positive edge clocking and no internal tri-states.
  • Scan test ready.
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors.
FUNCTIONAL DESCRIPTION

CSR: Contains all configuration registers used to monitor status and control the RTL functionality.

CONTROL DATA MAPPER: Multiplexes incoming control data into the blanking field.

VIDEO SAMPLER: Converts variable input pixels per clock (1, 2, 4 and 8) into a constant pixel per clock (PPC) rate. It also multiplexes the incoming video signals (hsync, vsync, video_de, video_data and vsync_detect) according to respective PPC.

LANE DISTRIBUTION: Distributes the incoming pixel data across multiple lanes.

PACKER: Packs the incoming pixel data based on the color space and color depth of the video stream.

LINK FSM: Tracks the transmitter FSM flow and controls the transmission of training patterns and normal video data.

SCRAMBLER: Scrambles the lane data for EMI reduction prior to 8b/10b encoding on the transmitter.

ENCODER 8B/10B: Converts incoming 8bit data into 10bit data to achieve DC balance.

LANE SKEW: Inserts skew between the data lanes.

GEARBOX: Converts the constant 20bit input into variable 20bit, 40bit or 80bit parallel output lane data.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesSystem Clock FrequencyVideo Clock FrequencyLink Clock FrequencySerdes Clock Frequency
TSMC 28nm31.28K100MHz297MHz200MHz200MHz
SMIC 40nm33.10K100MHz297MHz200MHz200MHz
UMC 55nm57.60K100MHz297MHz200MHz200MHz

FPGA Device and FamilyLogic ResourcesSystem Clock FrequencyVideo Clock FrequencyLink Clock FrequencySerdes Clock Frequency
AMD-xcvu9p-flga2104-2L-e3710 LUT's100MHz297MHz200MHz200MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.