PCIe Gen 5/4/3 Analog PHY IP

High-Bandwidth Serial Interconnect

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech PCIe Gen 5/4/3 Analog PHY IP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. High-performance analog front-ends engineered for the most demanding high-speed connectivity standards. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Broad Foundry Support: Silicon-proven and optimized for leading foundries including TSMC, SMIC, UMC, and GlobalFoundries.

Superior Signal Integrity: Integrated adaptive equalizers (CTLE, DFE) and advanced PLL architectures to overcome significant channel loss.

Functional Safety Ready: Developed with ISO 26262 standards in mind, providing the reliability required for automotive and industrial missions.

Ultra-Low Power & Area: Industry-leading PPA (Power, Performance, Area) metrics achieved through meticulous circuit design and layout.

FEATURES

Fully compliant with PCI Express Base Specifications 5.0, 4.0, 3.1, 2.1, and 1.1.
Supports data rates up to 32 GT/s per lane with multi-protocol support (PCIe, CXL).
Configurable lane widths (x1, x2, x4, x8, x16) with bifurcation and lane-reversal support.
State-of-the-art signal integrity: 3nd-gen adaptive FFE, CTLE, and 5-tap DFE to support >36dB channel loss.
Integrated PIPE 5.x interface with support for low-pin-count and high-performance modes.
Low-jitter fractional-N PLL architecture with fast lock times and multi-clock reference support.
Comprehensive power management: Support for L0s, L1, L1 substates (L1.1, L1.2), and L2/L3 states.
Advanced diagnostics: Real-time on-chip eye monitor, PRBS generator/checker, and BER testing.
ASIL-B/D functional safety ready for automotive and high-reliability industrial applications.

LICENSING OPTIONS

Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.

DELIVERABLES

GDSII Layout (Hard Macro).
LEF Abstract for Place & Route.
CDL Netlist for LVS and Simulation.
LIB (.lib) Timing, Power, and Noise Models.
Verilog Behavioral/Functional Models.
Integration Guide and Application Notes.
Characterization and Simulation Reports.
LVS, DRC, and ERC Verification Reports.
ISO 26262 Safety Manual (SAM) and FMEDA (for Automotive).