The SivaKali Tech SPACEWIRE CONTROLLER IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.
COMPETITIVE ADVANTAGE
Production Proven: Validated in silicon and FPGA across diverse applications.
Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.
Expert Support: Direct access to senior design engineers for rapid integration assistance.
Flexible Deliverables: Available as synthesizable source code or optimized netlists.
FEATURES
Implemented in Unencrypted Verilog, VHDL and SystemC
Compliant with ECSS-E-ST-50-12C Standard.
Supports speeds between 2 Mb/s and 400 Mb/s.
Supports sending packets of information from a source node to a specified destination node
Full‐duplex point‐to‐point serial data communication links.
Supports Data‐Strobe (DS) encoding.
Supports Flow control and link Initialization.
Includes Time-Codes support Arbitration schemes supported:
Priority based
Round‐robin
Random arbitration
First come first served
On-the-fly protocol and data checking.
Notifies the testbench of significant events such as transactions, warnings, and protocol violations.
Status counters for various events on bus.
SpaceWire Design IP comes with complete testsuite to verify each and every feature of SpaceWire specification.
FUNCTIONAL DESCRIPTION
CORE: Core module interconnects all the sub-modules in the Spacewire Controller IIP. Ports of core module are the top level ports for the Spacewire Controller IIP.
CSR: CSR Module has all the configuration registers. The contents of configuration registers are decoded and assigned to its respective output ports based on its functionality.
TFSM: TFSM Module is responsible for driving Spacewire controller frames.
RFSM: RFSM Module is responsible for sampling Spacewire controller frames.
ASIC AND FPGA IMPLEMENTATION
ASIC Technology
Logic Resources
Clock Frequency
TSMC 12nm
19.34K
50MHz
TSMC 28nm
12.28K
50MHz
TSMC 90nm
17.09K
50MHz
TSMC 130nm
17.09K
50MHz
TSMC 180nm
18.16K
50MHz
UMSC 55nm
21.49K
50MHz
SMIC 40nm
12.87K
50MHz
GF 180nm
13.60K
50MHz
FPGA Device and Family
Logic Resources
Clock Frequency
AMD-xcvu9p-flga2104-2L-e
988 LUT's
50MHz
LICENSING OPTIONS
Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.
