PWM IP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech PWM IP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. The backbone of system control and peripheral connectivity for any SoC. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Ultra-Low Gate Count: Extremely efficient implementation, negligible impact on total SoC area.

Simple Integration: Standard AMBA (APB/AHB) or AXI-Lite interfaces for plug-and-play system connectivity.

Proven Reliability: Thousands of production deployments ensuring rock-solid stability.

Driver Support: Includes bare-metal and Linux drivers to accelerate software development.

FEATURES

Supports 2 independent timers each of 32 bit.
Supports to generate square waveform with equal high and low period
Supports to generate rectangular waveform based on duty cycle
Supports configurable duty cycle
Supports up/down counting modes.
Supports configurable counter width.
Supports pulse generation after counting maximum value of 32’hFFFFFFF
Supports to generate a pulse after an interval
Automatically reload value support.
Supports to hold count value
Supports halting and resuming Timer.
Cascaded mode of operation support.
Supports enabling and disabling of interrupts.
Fully synthesizable.
Static synchronous design.
Positive edge clocking and no internal tri-states.
Scan test ready.
Simple host interfaces enable straightforward integration with microcontrollers and application processors.

FUNCTIONAL DESCRIPTION

CSR: CSR module has the set of registers used to configure GPIO core, log the GPIO status, program the timeout value for Host and register to store the GPIO data.

CORE: Core module interconnects all the sub-modules in the Peripheral IP. Ports of core module are the top level ports for the Peripheral IP and the Core Module acts as the central interconnect hub.

PRESCALAR: The Prescaler module is used to generate a clock enable output to Timer to count for number of clock cycles. It is used to extend the range of Timers.

REGS: The Regs Module has the load register, count register and control register for each Timer individually.

TIMER: The Timer modules provides output which sets the time period and the next timer sets the high time for PWM output.

PWM: The PWM Module receives pwm enable signals from two consecutive Timers. The two Timers will be counting and from the count value, Pulse Width Modulated (PWM) output is calculated.

ASIC AND FPGA IMPLEMENTATION

ASIC Technology	Logic Resources	Clock Frequency
TSMC 28nm	35.14K	100MHz
UMSC 55nm	63.77K	100MHz
SMIC 40nm	37.03K	100MHz

FPGA Device and Family	Logic Resources	Clock Frequency
AMD-xcvu9p-flga2104-2L-e	10628 LUT's	100MHz

LICENSING OPTIONS

Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.

DELIVERABLES

Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.