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MIPI DEBUG TS IIP

MIPI DEBUG Target System IIP

MIPI DEBUG TS IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech MIPI DEBUG TS IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Ideal for mobile, automotive, and IoT applications requiring high-bandwidth camera and display interfaces. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Low Power & High Efficiency: Optimized for mobile and battery-operated devices with advanced power gating and low-leakage architecture.

Silicon Proven: Validated on leading foundry nodes (5nm, 7nm, 12nm, 28nm), ensuring reduced integration risk.

Comprehensive Support: Full compliance with latest MIPI Alliance specifications, including CSI-2, DSI-2, and I3C.

Flexible Licensing: Cost-effective, royalty-free licensing models compared to restrictive tier-1 vendor options.

FEATURES
  • MIPI DEBUG TS v1.1.
  • Compliant with MIPI Debug version 1.1 specification.
  • Full MIPI Debug functionality.
  • Support full I3C Slave with Hot Join, IBI, DAA and HDR mode.
  • Full Link and Network/Transport layer.
  • Support Network adaptors for following,
  • SPP
  • STP
  • SAM
  • TWP
  • UART
  • Supports up to 16 Network Adaptors.
  • Fully synthesizable.
  • Static synchronous design.
  • Positive edge clocking and no internal tri-states.
  • Scan test ready.
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors.
FUNCTIONAL DESCRIPTION

CORE: CORE module interconnects all the main modules in the MIPI DEBUG TS IIP (CSR, I3C SLAVE, NETWORK LAYER). Ports of core module are the top level ports for the MIPI DEBUG TS IIP.

CSR : CSR module holds control, status, interrupt, configuration registers for the MIPI DEBUG TS IIP which can be accessed via AMBA/Custom interface.

I3C SLAVE : SLAVE module interconnects the I3C SLAVE releated sub-modules (SFSM, HDR Exit Restart, STOP, START).

SFSM: SFSM module process MIPI I3C commands once Start is detected. FSM responds to MIPI I3C commands (ACK/NACK for Write & Read transfer and Read data for read transfer) only if Slave address is matched with the address driven on the MIPI bus by the Master. The Slave FSM module includes Legacy I2C write/read transactions, I3C SDR transaction, Hot Join transaction, In Band Interrupt transaction, I3C HDR DDR transaction, Error detection functionalities.

HDR Exit Restart module: The HDR Restart Pattern used to send multiple messages in HDR Mode. When the I3C Bus is in a HDR Mode, an HDR Command can be sent to or from a Slave, and the HDR Restart Pattern can be used to send another HDR transfer continuosly, without exiting the current HDR Mode between the HDR Commands. All I3C Slaves shall detect and respond to the HDR Restart Pattern. HDR exit pattern is used to leave the HDR mode, and entering back to SDR mode. All I3C slaves shall detect and respond to the HDR exit pattern.

STOP: All transitions terminates with stop condition. Stop is detected based on SCL and SDA line. When SDA line goes from LOW to HIGH and SCL remains high is considered as the Stop condition. Master can terminate any transfers by initiating stop and it is detected by the Slave.

START: Initially SCL and SDA lines remains High, all transactions begin with a START condition. Start module detects the start condition on bus based on SDA and SCL line. A HIGH to LOW transition on the SDA line while SCL is HIGH defines a START condition Master initiates the start, it is detected by Slave. At certain condition (in case of hot join and IBI) Slave can initiate start. Start module detects the start condition on bus based on SDA and SCL line. A HIGH to LOW transition on the SDA line while SCL is HIGH defines a START condition. Repeated start condition is same as start condition, it is detected before stop condition. We can continue the further transfers without stop.

NETWORK LAYER : NETWORK LAYER interconnects the Adaptors and process the DEBUG CCC, DEBUG Opcodes, DEBUG IBI and MIPI Adaptors Write and Read transactions.

ADAPTOR : This module have the IB FIFO, OB FIFO and Session Management State machine for MIPI Adaptors.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesSystem Clock FrequencyProtocol Clock Frequency
TSMC 28nm51.07K800MHz12.5MHz

FPGA Device and FamilyLogic ResourcesSystem Clock FrequencyProtocol Clock Frequency
AMD Virtex Ultrascale+51685 LUT's100MHz12.5MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.