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Octal SPI Master IIP

OCTAL Serial Peripheral Interface Master IIP

Octal SPI Master IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech Octal SPI Master IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. The backbone of system control and peripheral connectivity for any SoC. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Ultra-Low Gate Count: Extremely efficient implementation, negligible impact on total SoC area.

Simple Integration: Standard AMBA (APB/AHB) or AXI-Lite interfaces for plug-and-play system connectivity.

Proven Reliability: Thousands of production deployments ensuring rock-solid stability.

Driver Support: Includes bare-metal and Linux drivers to accelerate software development.

FEATURES
  • Full Octal SPI Master Functionality
  • Fast frequency support(Up to 133MHz)
  • Compliant to the SPI de-facto standard
  • Single, dual, quad and octal serial data lines
  • Software programmable transmission formats (CPOL and CPHA)
  • Up to 16 slaves supported under master control
  • Configurable SPI transfers
  • Fast sampling clock input for the SPI transfers
  • FIFOs used for transferring data (configurable depth)
  • Full duplex operation
  • LSB or MSB mode
  • 8-bit, 16-bit, 24-bit and 32-bit synchronous serial transmission
  • Software programmable SCLK rate
  • Supports DMA/HCI (Host controller Interface) mode of operation
  • Interrupt control
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors
FUNCTIONAL DESCRIPTION

CORE: Core Module interconnects all the sub-modules in the SPI IP. Ports of core module are the top level ports for the SPI IP.

PRESCALER: Prescaler Module is used to divide the system clock based on the given prescaler value to drive the serial clock input for SPI.

FSM: FSM Module generates the SPI transcations on SPI Master based on commands from CSR block. This blocks implements all the features of SPI specifications.

ARB: ARB Module implements the arbiter to arbit between HCI and FSM access to CSR block.

HCI: HCI Module implements SPI Host controller FSM. The HCI FSM fetches the data from descriptor memory like SPI commands and transmit data bytes and it loads sampled read data bytes into descriptor memory.

XIP: XIP Module implements XIP/AIP mode operation with zero software overhead. XIP Module consists of functionality of both XIP and AIP mode. In XIP (Xecute In Place mode) executing the code directly from the serial flash memory .It will directly read from the Flash memory.In AIP (Access In Place) mode has both read and write operation will execute.It will write data into the flash device.XIP module is connected with soc Slave interface.

BOOT: Boot Module allows the host to read the data from the flash device after the power is on or after the hardware reset is done. It reads the data from the flash device without read command and address

CSR: CSR Module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesSystem Clock FrequencyDMA Clock FrequencySerial Clock Frequency
TSMC 12nm25.77K100MHz100MHz50MHz
TSMC 180nm26.04K100MHz100MHz50MHz
TSMC 130nm25.22K100MHz100MHz50MHz
TSMC 90nm25.22K100MHz100MHz50MHz
TSMC 28nm17.45K100MHz100MHz50MHz
GF 180nm18.28K100MHz100MHz50MHz
SMIC 40nm18.65K100MHz100MHz50MHz
UMSC 55nm30.36K100MHz100MHz50MHz

FPGA Device and FamilyLogic ResourcesClock Frequency
AMD-xcvu9p-flga2104-2L-e51685 LUT's100MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.