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SAE J1850 IIP

SAE J1850 IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech SAE J1850 IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Production Proven: Validated in silicon and FPGA across diverse applications.

Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.

Expert Support: Direct access to senior design engineers for rapid integration assistance.

Flexible Deliverables: Available as synthesizable source code or optimized netlists.

FEATURES
  • Compliant with SAE J1850-2015 Specifications
  • Full SAE J1850 functionality
  • Supports Type0,1,2,3 frame formats
  • Supports Hardware CRC as per specs
  • Supports multi byte transmit and reception
  • Supports IRQ after frame transmission
  • Supports both VPW and PWM Bus symbols
  • Supports BREAK symbol generation
  • Supports Collision Detection
  • Dedicated Register for Symbol Timing Adjustments
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the SAE_J1850 IP. Ports of core module are the top level ports for the SAE_J1850 IP.

PRESCALER: Prescaler module is used to divide the system clock based on the given prescaler value to derive the serial clock input for SAE_J1850.

TFSM: TFSM module controls the complete transmit sequence of J1850 frames including arbitration,timing.This blocks implements all the features of SAE_J1850 specs.

RFSM: RFSM module controls the complete receive sequence including start detection,bit sampling,frame validation and error handling.This blocks implements all the features of SAE_J1850 specs.

CSR: CSR module has all the Control registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

CRC: CRC Module calculates the CRC value based on the input data received from the FSM Module. Calculated CRC value sends to the FSM Module. Based on this CRC values the status registers are compared.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesSystem Clock FrequencyProtocol Clock Frequency
TSMC 28nm8.31K20MHz2MHZ
UMSC 55nm12.26K20MHz2MHZ
SMIC 40nm7.44K20MHz2MHZ

FPGA Device and FamilyLogic ResourcesSystem Clock FrequencyProtocol Clock Frequency
AMD-xcvu9p-flga2104-2L-e204334 LUT's20MHz2MHZ

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.