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ARINC419 CONTROLLER IIP

Aeronautical Radio Incorporated 419 Controller IIP

ARINC419 CONTROLLER IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech ARINC419 CONTROLLER IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Engineered for ADAS, infotainment, and vehicle control units (ECUs). Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Automotive Grade: Developed with ISO 26262 functional safety processes (ASIL-B/D Ready).

High Reliability: Robust error handling and fault tolerance for mission-critical vehicle networks.

Legacy & Future: Supports both classic protocols and modern, high-speed automotive networking standards.

Cost Effective: Affordable licensing for high-volume automotive production runs.

FEATURES
  • Implemented in Unencrypted Verilog, VHDL and SystemC
  • Supports with ARINC REPORT 419 -3.
  • Supports 32 bit words containing a 24 bit data portion containing the actual information, and an 8 bit label describing the data itself.
  • Supports Transmission rates at 11 ± 3.5 kbps.
  • Supports Bipolar Return-to-Zero encoding format.
  • Supports following data types
    • Binary – BNR – Transmitted in fractional two’s complement notation
    • Binary Coded Decimal – BCD – Numerical subset of ISO Alphabet No. 5
    • Maintenance Data and Acknowledgement - Requires two-way communication
  • Supports duplex or two-way communication in Maintenance Data and acknowledgement between source and sink
  • Supports all types of error insertion/detections as given below:
    • Parity Errors
    • Word count errors
    • Synchronization errors
    • Invalid label errors
  • Notifies the test bench of significant events such as transactions, warnings, and protocol violations
  • Status counters for various events.
  • Built in functional coverage analysis.
  • FIFO depth programmable.
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the ARINC419 Controller IP. Ports of core module are the top level ports for the ARINC419 Controller IP.

PRESCALER: Prescaler module is used to divide the system clock based on the given prescaler value to derive the serial clock input for transmission and reception of ARINC419 Controller.

SOURCE_FSM: Source fsm module implements ARINC419 Source controller FSM

SINK_FSM: Sink fsm module implements ARINC419 Sink controller FSM

CSR: CSR module has all the Control and status registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality. This block contains interrupt enable and status registers.

ASIC AND FPGA IMPLEMENTATION
TSMC 28nm7.11K50MHz
TSMC 12nm10.44K50MHz
TSMC 90nm10.32K50MHz
TSMC 130nm10.32K50MHz
TSMC 180nm10.98K50MHz
GF 180nm7.53K50MHz
SMIC 40nm7.74K50MHz
UMC 55nm12.36K50MHz

FPGA Device and FamilyLogic ResourcesClock Frequency
AMD-xcvu9p-flga2104-2L-e1185 LUT's50MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.