ETHERNET 10BASET1S PCS IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech ETHERNET 10BASET1S PCS IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Designed for data center, enterprise networking, and industrial automation environments. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Low Latency Architecture: Engineered for real-time applications with deterministic latency, ideal for TSN (Time Sensitive Networking).

Scalable Performance: Seamless migration paths from 10M to 800G, supporting a wide range of networking requirements.

Robust Compliance: Fully compliant with IEEE 802.3 standards, ensuring interoperability with standard network equipment.

Integrated Offload: Advanced TCP/UDP offload engines (TOE) to reduce host processor overhead.

FEATURES

Supports ETHERNET 10BASE-T1S PCS compliant with IEEE standard 802.3-2022 clause 147
Supports MII interface with 10Mbps speed
Supports Self-synchronizing Scrambler/Descrambler
Supports 4b/5b Encoding/Decoding
Supports DME(Differential Manchester Encoding)
Supports full duplex and half duplex operation
Supports PLCA (Physical layer Collision Avoidance)
Supports clause 98 auto-negotiation
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors

FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the ETHERNET 10BASET1S PCS IP. Ports of core module are the top level ports for the ETHERNET 10BASET1S PCS IP.

PCS TX FSM: PCS TX FSM module scrambles and encodes the scrambled data by encapsulating start,end and other delimiters.

TX DME: TX DME module is used to convert symbols to DME (Differential Manchester Encoding), and drive in the positive and negative TD pins.

TX HEARTBEAT: TX Heartbeat module is used to send the heartbeat command, when the multidrop is disabled and MII data transmission starts.

TX MUX: TX MUX module is used to selects between normal data or Topology Discovery pulses based on topology discovery enable.

PCS RX FSM: PCS RX FSM module is used to implements the descrambler logic and decode symbols as mii data.

RX DME: RX DME module is used to implement the synchronization for received data with Edge detection.

RX HEARTBEAT: RX Heartbeat module is used to implements receive path heart beat handling.

PCS ALIGN: PCS Align module is used to lock the start pattern to aligned 5bit symbols from the received stream data.

TOPOLOGY DISCOVERY: Topology Discovery module is used to drive transmit positive(txp) and transmit negative(txn) pulses based on Topology discovery enable.

PLCA DATA: PLCA Data module is used to hold the data and asserts Backpressure (COL) until the commit command receive.

PLCA CTRL: PLCA CTRL module is used to sends the PLCA command to the PLCA data FSM and process the COMMIT command based on the transmit opportunity.

PLCA STATUS: PLCA STATUS module is used to indicate the PLCA status csr module.

PMD CTRL: PMD CTRL module is used to manages the power states (Sleep vs Active) and ensures the Line Driver is only enabled when the PHY is stable.

CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

US TIMER: US TIMER register is used to control the integer and fractional part of the divider.

MAC INTERFACE: MAC INTERFACE module supports the MII MAC TX and RX with 10Mbps speed.

ASIC AND FPGA IMPLEMENTATION

ASIC Technology	Logic Resources	Clock Frequency	PCS Clock Frequency	MII Clock Frequency
TSMC 28nm	56.78K	25MHz	2.5MHz	2.5MHz
UMSC 55nm	56.78K	25MHz	2.5MHz	2.5MHz
SMIC 40nm	56.78K	25MHz	2.5MHz	2.5MHz

FPGA Device and Family	Logic Resources	Clock Frequency	PCS Clock Frequency	MII Clock Frequency
Kintex 7,9467 LUT'S	25MHz	2.5MHz	2.5MHz

LICENSING OPTIONS

Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.

DELIVERABLES

Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.