CORE: Core module interconnects all the sub-modules in the LPDDR5X Controller IP. Ports of core module are the top level ports for the LPDDR5X Controller IP.
ARBITER: Arbiter module implements arbitration for multi-channel and between same channels write and read. This module will get inputs from SoC data interface and process to write data FIFO, Read data FIFO and Command FIFO.
WRITE DATA FIFO: Write data fifo stores the write data in write operation which is coming from soc data interface.
READ DATA FIFO: Read data fifo stores the read data in read operation which is coming from dfi interface.
COMMAND FIFO: Command fifo stores the write/read commands or address related information.
LPDDR5X CONTROLLER FSM:
This block consists of several sub modules listed below:
COMMAND FIFO PROCESSOR: Command fifo processor reads the command fifo data, decodes command fifo data and issues commands to FSM. Also pushes length to read response fifo which will be used in read operation.
ATIMER: Activate timer module is used to implement timers for maximum active time of a particular bank. For every write and read related operations the bank must be activate before processing those commands. This module gets bank and activate information from the FSM module and maximum bank activate time is decided by refresh requirement, configured from csr module. Based on this, It will close the activated banks.
FSM: LPDDR5X Controller FSM starts to process once the commands are received from Command FIFO processor and CSR Modules. Based on the received commands, the LPDDR5X Controller FSM process Activate, Write, Read, Mode Register operations.
The functionalities of the LPDDR5X Controller FSM module include:
- Initialization Process
- Handling Memory Read/Write/Mask write
- Handling Mode Register Read/Write
- Activate and Precharge operations
- Self-Refresh and Power Down Modes
- Refresh Operations
COMMAND DRIVER: Command driver block gets chip and address from FSM module, this block also implements latency logic. Once latencies are satisfied cs and address will be driven to DFI. Command driver block generates write enable to data driver, read enable to data receiver in respective operations. Also this block generates wck enable incase of wr/rd commands received from FSM.
WCK DRIVER: WCK Driver module gets wck sync enable information from the command driver module and latency information from the CSR module. WCK synchronization happens for all write, read, MRR and masked write operations.
DATA DRIVER: Data driver module gets write enable and encoded write command value information from the command driver module. The data driver module collects data from the Write data FIFO. This module gets latency information from the CSR module. Once latency is satisfied, this module drives write data to dfi write data interface.
DATA RECEIVER: Data receiver module gets read enable and encoded read command value information from the command driver module. This module gets latency information from the CSR module. Once latency is satisfied, this module drives read enable after data latency the module samples read data from dfi read data interface when corresponding valid is high. Once entire burst of the data are sampled the data are sent to the Read data FIFO.
CSR: CSR Module has all the mode registers and timer configuration registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality. The registers can get its data from both the internal and external system interface.
