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TileLink To APB Bridge IIP

TileLink To APB Bridge IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech TileLink To APB Bridge IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Engineered for ADAS, infotainment, and vehicle control units (ECUs). Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Automotive Grade: Developed with ISO 26262 functional safety processes (ASIL-B/D Ready).

High Reliability: Robust error handling and fault tolerance for mission-critical vehicle networks.

Legacy & Future: Supports both classic protocols and modern, high-speed automotive networking standards.

Cost Effective: Affordable licensing for high-volume automotive production runs.

FEATURES
  • Compliant with SiFive TileLink specification version 1.8.1
  • Compliant with AMBA APB3 , AMBA APB4 specification
  • Translates Tilelink transactions into APB transactions
  • Support for data phase timeout when APB interface does not send response
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors
  • This core achieves ASIL B and can be made to achieve ASIL D as per ISO26262
FUNCTIONAL DESCRIPTION

TileLink2 APB Bridge Core: Acts as the main conversion logic that translates TileLink transactions into APB protocol transactions. It manages address, control, and data signal mapping and ensures proper timing and handshake between the two protocols.

TileLink Slave Interface: Receives TileLink protocol requests such as read and write transactions from the TileLink master. It decodes the incoming TileLink signals and forwards the transaction information to the bridge core for further processing.

APB Master Interface: Generates APB compliant signals such as PADDR, PWRITE, PSEL, PENABLE, and PWDATA based on the converted TileLink request. It communicates with APB slave peripherals and returns response data back through thebridge to the TileLink side.

ASIC AND FPGA IMPLEMENTATION
Target NodeMax FrequencyArea/Resources
7nm FinFET> 1.2 GHz< 0.1 mm2
28nm HPC+> 800 MHz< 0.25 mm2
FPGA (UltraScale+)> 400 MHz~5,000 LUTs

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.