HDMI eARC Receiver IIP

• HDMI eARC Receiver IIP
• Fully compliant with the HDMI eARC Receiver specification as defined in the HDMI version 2.1b specification and ensures standard-adherent operation across all supported configurations.
• Supports configurable audio channel count from 2 to 32 channels.
• Supports variable audio sample words lengths of 16-bit, 20-bit and 24-bit.
• Supports audio sample rates from 32kHz to 192kHz.
• Supports the reception of the following encrypted and unencrypted audio formats:
  • 2-channel L-PCM.
  • Multi-channel L-PCM.
  • IEC 61937(compressed audio).
  • One bit audio.
• Supports single-ended non-differential split outputs for flexible integration.
• Performs bi-phase mark decoding and falling-edge demodulation.
• Dynamically supports seamless Audio Format Change operations.
• Manages the following critical functions over the eARC Common Mode Data Channel:
  • Discovery and Disconnect protocols.
  • Heartbeat monitoring.
  • Status bits transmission/reception.
  • Audio Latency Control.
  • Capabilities Data Structure exchange
• Supports the extraction of audio channel status and user bits.
• Extracts and processes ACP, ISRC1 and ISRC2 U-bit messages structures.
• Incorporates Error Correcting Code(ECC) decoding and robust error correction on both the eARC Common mode data channel and the high-speed differential mode channel.
• Fully synthesizable.
• Static synchronous design.
• Positive edge clocking and no internal tri-states.
• Scan test ready.
• Simple host interfaces enable straightforward integration with microcontrollers and application processors.

CSR: Contains all configuration registers used to monitor status and control the RTL functionality.

CONTROL DECODER: Decodes the incoming biphase-mark encoded data from the Common mode data channel and passes the extracted information to the Control Receive FSM.

CONTROL RECEIVE FSM: Validates incoming messages and forwards critical discovery, capability and status information to the appropriate internal logic for processing.

CONTROL TRANSMIT FSM: Formats the required response messages and transmits control responses over the control channel in strict accordance with eARC protocol timing rules.

CONTROL ENCODER: Converts the formatted payload from the Control transmit FSM into a serialized bit-stream for transmission back to the source device.

DATA DECODER: Processes the incoming high-speed differential audio stream and validates the data integrity using embedded synchronization patterns.

DATA RECEIVE FSM: Manages the overall state machine for the reliable reception, buffering and routing of the high-bitrate audio data payloads.

PRESCALAR: Divides the system clock based on a configurable prescaler value to derive the necessary serial clock. It also handles clock recovery by extracting the internal bit clock directly from the incoming data stream transitions.

• Single Site license for regional development teams.
• Multi-Site license for global corporate deployments.
• Single Design license for specific project cost-efficiency.
• Unlimited Design license for high-volume product roadmaps.

• Complete Verilog/VHDL/SystemC Source Code.
• UVM-compliant verification environment with a comprehensive test suite.
• Production-ready synthesis, Lint, and CDC scripts.
• IP-XACT RDL generated address maps.
• Standard-compliant firmware and Linux/C driver packages.
• Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.