The SivaKali Tech SPI AXI Bridge IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. The backbone of system control and peripheral connectivity for any SoC. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.
COMPETITIVE ADVANTAGE
Ultra-Low Gate Count: Extremely efficient implementation, negligible impact on total SoC area.
Simple Integration: Standard AMBA (APB/AHB) or AXI-Lite interfaces for plug-and-play system connectivity.
Proven Reliability: Thousands of production deployments ensuring rock-solid stability.
Driver Support: Includes bare-metal and Linux drivers to accelerate software development.
FEATURES
Compliant with the SPI Block Guide 4.01 standard.
Full SPI Slave functionality.
Converts SPI Transactions into AXI write or read instructions
Allows external devices to access the internal AXI Bus
Useful for updating device software from and external device
Useful for reading internal memory mapped registers and memory
Supports Mailbox Read/Write functionality
Supports AXI Master Read/ Write capability
Supports AXI Slave
Supports monitoring of erroneous AXI transfers and reports error to the system
Supports Single/Dual/Quad/Octal SPI Data line
Supports flexible transfer format to work with slower interfaces Supports address width of 8,16,24 and 32 bits
Supports following frames for SPI
Sleep Frame
Wakeup Frame
Write Frame
Read Frame
Extended Register Write Frame
Extended Register Read Frame
Extended Register Write Long Frame
Extended Register Read Long Frame
Extended Register Write Long Long Frame
Extended Register Read Long Long Frame
Support single and burst transfer mode for SPI
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors
FUNCTIONAL DESCRIPTION
CORE: Core Module interconnects all the sub-modules in the SPI IP. Ports of core module are the top level ports for the SPI IP.
FSM: FSM Module generates the SPI transcations on SPI Master based on commands from CSR block. This blocks implements all the features of SPI specifications.
ARB: Arbiter Module selects the read write operation of DMA and FSM module to access the CSR module.
DMA: DMA Module is used to write/read the data to/from DMA memory through SoC master interface.
CSR: CSR Module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.
ASIC AND FPGA IMPLEMENTATION
ASIC Technology
Logic Resources
System Clock Frequency
DMA Clock Frequency
Serial Clock Frequency
TSMC 12nm
24.60K
100MHz
100MHz
50MHz
TSMC 28nm
15.93K
100MHz
100MHz
50MHz
TSMC 90nm
24.60K
100MHz
100MHz
50MHz
TSMC 130nm
23.46K
100MHz
100MHz
50MHz
TSMC 180nm
24.29K
100MHz
100MHz
50MHz
UMSC 55nm
28.71K
100MHz
100MHz
50MHz
SMIC 40nm
17.15K
100MHz
100MHz
50MHz
GF 180nm
17.71K
100MHZ
100MHZ
50MHZ
FPGA Device and Family
Logic Resources
Clock Frequency
AMD-xcvu9p-flga2104-2L-e
51685 LUT's
100MHz
LICENSING OPTIONS
Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.
