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ARINC664 SWITCH IIP

ARINC664 SWITCH IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech ARINC664 SWITCH IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Engineered for ADAS, infotainment, and vehicle control units (ECUs). Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Automotive Grade: Developed with ISO 26262 functional safety processes (ASIL-B/D Ready).

High Reliability: Robust error handling and fault tolerance for mission-critical vehicle networks.

Legacy & Future: Supports both classic protocols and modern, high-speed automotive networking standards.

Cost Effective: Affordable licensing for high-volume automotive production runs.

FEATURES
  • Fully Compliant with ARINC664 Part 7 (AFDX) Specification
  • Compliant with IEEE Standard 802.3-2022 Specification for MAC
  • Supports Full-duplex 10M/100M Ethernet interfaces
  • Supports MII/RMII Physical Layer device (PHY) Interfaces
  • Supports different data rate for each port
  • Supports configuration VL (Virtual Link) Table
  • Supports up to 1024 Virtual Links (Configurable to 64K)
  • Supports customized number of ports
  • Deterministic L2 Routing based on 16-bit VL ID
  • Hardware based BAG(Bandwidth Allocation Gap) enforcement (1ms to 128ms)
  • Jitter monitoring and policing (< 500us precision)
  • Max frame length (LMAX) enforcement per VL
  • Dual Queue Qos (High Priority/Low Priority) per port
  • Supports Round Robin traffic shaping
  • Shared memory architecture of 128 bit wide memory bus
  • Supports frame filtering and traffic policing
  • Supports frame filtering mechanism as per the ARINC 664 Specification or the below, Ethernet frame size is greater than or equal to 64 (minimum frame size) and less than or equal to 1518 (maximum frame size) Frame Check Sequence validity(FCS) Frame length error Ethernet line size is greater than or equal to 84 and less than or equal to 1538
  • Supports Virtual Link Traffic Shaping (BAG – Bandwidth Allocation Gap)
  • Ultra low latency and compact implementation
  • Supports Programmable Inter Packed Gap(IPG) and Preamble length
  • FCS generation supported
  • Independent TX and RX Maximum Transmission Unit (MTU)
  • Configurable Transmit and Receive FIFOs
  • Provides detailed statistics as per the specification including VL (Virtual Link) message count
  • Supports MDIO (Clause 22 and Clause 45) Interface
  • In house UNH compliance tested
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the ARINC664 SWITCH IP. Ports of core module are the top level ports for the ARINC664 SWITCH IP.

INGRESS: Ingress module handles the in-out port mapping of the ingress mii, ingress process,ingress dma and ingress fetch modules.

INGRESS MII: The ingress mii module receives the RX packet and extracts the VL, serial number and frame length and sends output to the ingress process.

INGRESS PROCESS: Ingress process module Processes the packet based on the lookup search output and sends the frame to ingress dma module.

INGRESS DMA: Ingress dma module performs handling of descriptors from ingress fetch and grant from crossbar memory and writes data to the crossbar memory arbiter.

INGRESS FETCH: Ingress fetch module provides descriptors to ingress dma for storing data in crossbar memory arbiter and generates input for crossbar reference manager.

EGRESS: All transmitter process done here for each ports. The Egress has below modules for transmitting process.

EGRESS ARBITER: This module implements egress queues and the associated round-robin arbitration logic.

EGRESS DMA: This module implements DMA logic to request packet from crossbar memory and store that in internal fifo. The data further gives the frame to MII transmit process.

EGRESS FREE: Egress free module performs handling of Egress link pointer.

EGRESS MII: Egress mii implements the MII transmitter logic.

LOOKUP ENGINE: Lookup engine uses a static lookup table based on the Virtual Link ID(VLID). It is shared by all the Ethernet ports we have in AFDX system. The engine extracts the 16 bit VLID from the last two bytes of the incoming packet’s destination MAC address.

CROSSBAR FABRIC AND MEMORY ARBITER: Cross bar modules handles the in-out port mapping of the link list manager, Memory Arbiter and Reference Manager modules. It has big memory and its split into small chunks as 256 bytes to store the data.

CROSSBAR LINK LIST MANAGER: The Link List Manager typically maintains the descriptor list of the Cross bar Memory.

CROSSBAR MEMORY ARBITER: This Cross bar Memory Arbiter module Performs the write and read operation based on ingress and egress modules request using round robin fashion for all the ports.

CROSSBAR REFERENCE MANAGER: This Cross bar Reference Manager module used to maintain the available write pointers and clear the pointers when it is read from all the egress ports to forward the packets.

MDIO: The management interface is a simple two-wire, serial interface to connect management entity and a managed PHY for the purposes of controlling the PHY and gathering status from the PHY.

CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesSystem Clock FrequencyMAC Clock Frequency
TSMC 28nm76.46K125MHz25MHz
UMSC 55nm181.46K125MHz25MHz
SMIC 40nm128.46K125MHz25MHz

FPGA Device and FamilyLogic ResourcesSystem Clock FrequencyMAC Clock Frequency
xcku040-ffva1156-2-e61075 LUT's125MHz25MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.