AHB2AXI BRIDGE IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech AHB2AXI BRIDGE IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Forming the high-speed communication backbone of complex System-on-Chips. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Deadlock Free: Robust routing logic prevents system hang-ups under heavy load conditions.

Low Latency Bridging: Efficient clock domain crossing and protocol conversion with minimal cycle overhead.

High Frequency: Pipelined architecture designed to close timing at high clock frequencies in modern nodes.

Scalable: Easily configurable for simple bus fabrics or complex, multi-layer network-on-chip (NoC) implementations.

FEATURES

Compliant with AMBA AHB Specification
AMBA AHB2AXI Bridge allows connecting AHB Master to an AXI Slave.
Supports incrementing, wrapping and fixed burst transfers
Supports narrow transfers
Supports address/data phase timeout
Supports separate state machines to handle write and read and also to all responses
Supports below Configuration Parameters,

AXI data bus width and endianness
AHB data bus width (can be different than AXI data bus width)
AHB address bus width
Data width, base address and address space
Use of transfer response (HRESP) signal

Requires no run-time programming or initialization
HTML configuration tool generates Verilog parameters
Fully synchronous, scan-ready, LINT-clean design
Delivered with sample scripts, RTL testbench and sample test cases
Can be mapped to any ASIC or FPGA
Fully synthesizable
Positive edge clocking and no internal tri-states.
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors
Build in self test to test all locations in memory to identify damaged locations
This core achieves ASIL B and can be made to achieve ASIL D as per ISO26262

FUNCTIONAL DESCRIPTION

CORE: Core module performs all the below functionalities in the AHB2AXI BRIDGE IIP. Ports of core module are the top level ports for the AHB2AXI BRIDGE IIP.

AHB SLAVE: AHB Slave is used to respond to a read or write operation within a given address-space range. It accepts address and control from the master and returns data/response.

AXI MASTER: AXI Master is use to initiate read and write operations by providing an address and control information.

DATA ALLIGNER: Data Aligner is used to adjust the data positions and size between AHB and AXI formats.

AHB TRANSFER CONTROLLER: It controls and sequences incoming AHB read/write transactions inside the bridge.

AXI TRANSFER CONTROLLER: It generates and controls AXI protocol signals for each transfer.

ADDRESS DECODER: Address Decoder checks the AXI address and identifies the corresponding AHB slave based on the configured address ranges.

ASIC AND FPGA IMPLEMENTATION

ASIC Technology	Logic Resources	Clock Frequency
TSMC 28nm	2.35K	100MHz

FPGA Device and Family	Logic Resources	Clock Frequency
AMD-xcvu9p-flga2104-2L-e	391.66 LUT's	100MHz

LICENSING OPTIONS

Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.

DELIVERABLES

Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.