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HYPERBUS IP

HYPERBUS IP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech HYPERBUS IP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Production Proven: Validated in silicon and FPGA across diverse applications.

Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.

Expert Support: Direct access to senior design engineers for rapid integration assistance.

Flexible Deliverables: Available as synthesizable source code or optimized netlists.

FEATURES
  • Supports Hyperbus memory devices from all leading vendors.
  • Supports 100% of Hyperbus protocol standard Hyperbus specifications.
  • Supports all the Hyperbus commands as per the specs.
  • Supports 512 Mb HyperFlash and 64 Mb HyperRAM.
  • Supports 8-bit data bus (DQ[7:0])
  • Supports Read-Write Data Strobe (RWDS)
  • Supports Device Identification Registers.
  • Supports Configuration Registers.
  • Supports Double-Data Rate(DDR) - two data transfers per clock.
  • Supports Sequential burst transactions.
  • Supports following Configurable burst characteristics.
    • Wrapped burst length options - 128 Bytes (64 clocks) - 64 Bytes (32 clocks) - 32 Bytes (16 clocks) - 16 Bytes (8 clocks)
    • Linear burst
    • Hybrid option - one wrapped burst followed by linear burst
    • Wrapped or linear burst type selected in each transaction
  • Supports following Power Conservation Modes.
    • Interface Standby
    • Active Clock Stop
    • Deep Power-Down
  • Fully synthesizable
  • Scan test ready
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the Hyperbus IP. Ports of core module are the top level ports for the Hyperbus IP.

FSM: The FSM follows a sequenctial flow consisting of three main phases: Command Address phase, the Latency Phase and the data phase. It monitors the Read Write Data Strobe signal. The Hyperbus IP handles Linear Burst and Wrapped Burst modes.

CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesSystem Clock Frequency
TSMC 28nm24.04K50MHz

FPGA Device and FamilyLogic ResourcesClock Frequency
AMD-xcvu9p-flga2104-2L-e51685 LUT's187.25MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.